Improve performance for branchy code

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index e27aa823eeaad33022fa26edf9b49a41b6e85fcf..9e52d3d176a91ebeeb1faa1d427951edbf00e54b 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -65,6 +65,7 @@ public:
   void deliver_ipi(); // register an interprocessor interrupt
   bool running() { return run; }
   reg_t set_pcr(int which, reg_t val);
+  void set_fromhost(reg_t val);
   void set_interrupt(int which, bool on);
   reg_t get_pcr(int which);
   mmu_t* get_mmu() { return mmu; }
@@ -91,13 +92,12 @@ private:
   std::vector<insn_desc_t> opcode_store;
 
   void take_interrupt(); // take a trap if any interrupts are pending
-  void take_trap(reg_t pc, trap_t& t); // take an exception
+  void take_trap(trap_t& t); // take an exception
   void disasm(insn_t insn); // disassemble and print an instruction
 
   friend class sim_t;
   friend class mmu_t;
   friend class extension_t;
-  friend class htif_isasim_t;
 
   void build_opcode_map();
   insn_func_t decode_insn(insn_t insn);