Add writing to DCSR, DPC, DSCRATCH.

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 869873fffe7e9100e336f6229940de36aa6626b5..e0142995c1c09d8eb5ae6ce829738d4e8ec1dbeb 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -31,6 +31,19 @@ struct commit_log_reg_t
   reg_t data;
 };
 
+typedef struct
+{
+  uint8_t prv;
+  bool step;
+  bool debugint;
+  bool ebreakm;
+  bool ebreakh;
+  bool ebreaks;
+  bool ebreaku;
+  bool halt;
+  uint8_t cause;
+} dcsr_t;
+
 // architectural state of a RISC-V hart
 struct state_t
 {
@@ -61,6 +74,10 @@ struct state_t
   reg_t stvec;
   reg_t sptbr;
   reg_t scause;
+  reg_t dpc;
+  reg_t dscratch;
+  dcsr_t dcsr;
+
   uint32_t fflags;
   uint32_t frm;
   bool serialized; // whether timer CSRs are in a well-defined state