add load-reserved/store-conditional instructions

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index e452df251211163782424ed5417769051dc242de..f3b2f62cd69443d1eaa0c3cfd1fbb351143ebb3c 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -39,8 +39,6 @@ private:
   regfile_t<reg_t, NXPR, true> XPR;
   regfile_t<freg_t, NFPR, false> FPR;
   reg_t pc;
-
-  // counters
   reg_t cycle;
 
   // privileged control registers
@@ -58,9 +56,6 @@ private:
   uint32_t count;
   uint32_t compare;
 
-  // # of bits in an XPR (32 or 64). (redundant with sr)
-  int xprlen;
-
   bool run; // !reset
 
   // functions