Fix 2 trigger corner cases. (#229)

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index ace86f963959145e3e8a7227f4fa2e91f0395e71..fd90ce3da8943861569a4f35508f8dd4f07e0a27 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -135,8 +135,6 @@ struct state_t
       STEP_STEPPED
   } single_step;
 
-  reg_t load_reservation;
-
 #ifdef RISCV_ENABLE_COMMITLOG
   commit_log_reg_t log_reg_write;
   reg_t last_inst_priv;
@@ -188,13 +186,15 @@ public:
     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
     return ext >= 'A' && ext <= 'Z' && ((state.misa >> (ext - 'A')) & 1);
   }
+  reg_t pc_alignment_mask() {
+    return ~(reg_t)(supports_extension('C') ? 0 : 2);
+  }
   void check_pc_alignment(reg_t pc) {
-    if (unlikely(pc & 2) && !supports_extension('C'))
+    if (unlikely(pc & ~pc_alignment_mask()))
       throw trap_instruction_address_misaligned(pc);
   }
   reg_t legalize_privilege(reg_t);
   void set_privilege(reg_t);
-  void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
   void update_histogram(reg_t pc);
   const disassembler_t* get_disassembler() { return disassembler; }