[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / riscv.ac

diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 897b21fba563dbec25f26685af1b2b2169703920..00358fdbe098350f61616ea51b8ad92140c0df75 100644 (file)
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -8,8 +8,8 @@ AS_IF([test "x$enable_64bit" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported])
 ])
 
-AC_ARG_ENABLE([rvc], AS_HELP_STRING([--disable-rvc], [Disable instruction compression]))
-AS_IF([test "x$enable_rvc" != "xno"], [
+AC_ARG_ENABLE([rvc], AS_HELP_STRING([--enable-rvc], [Enable instruction compression]))
+AS_IF([test "x$enable_rvc" = "xyes"], [
   AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported])
 ])
 
@@ -18,7 +18,7 @@ AS_IF([test "x$enable_vec" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported])
 ])
 
-AC_ARG_ENABLE([icsim], AS_HELP_STRING([--disable-icsim], [Enable instruction cache simulator]))
+AC_ARG_ENABLE([icsim], AS_HELP_STRING([--enable-icsim], [Enable instruction cache simulator]))
 AS_IF([test "x$enable_icsim" = "xyes"], [
   AC_DEFINE([RISCV_ENABLE_ICSIM],,[Define if instruction cache simulator is enabled])
 ])