[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / riscv.ac

diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 9bb4f2faacdce74b83b058fb6da06367299c0b18..00358fdbe098350f61616ea51b8ad92140c0df75 100644 (file)
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -8,11 +8,21 @@ AS_IF([test "x$enable_64bit" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported])
 ])
 
-AC_ARG_ENABLE([rvc], AS_HELP_STRING([--disable-rvc], [Disable instruction compression]))
-AS_IF([test "x$enable_rvc" != "xno"], [
+AC_ARG_ENABLE([rvc], AS_HELP_STRING([--enable-rvc], [Enable instruction compression]))
+AS_IF([test "x$enable_rvc" = "xyes"], [
   AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported])
 ])
 
+AC_ARG_ENABLE([vec], AS_HELP_STRING([--disable-vec], [Disable vector processor]))
+AS_IF([test "x$enable_vec" != "xno"], [
+  AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported])
+])
+
+AC_ARG_ENABLE([icsim], AS_HELP_STRING([--enable-icsim], [Enable instruction cache simulator]))
+AS_IF([test "x$enable_icsim" = "xyes"], [
+  AC_DEFINE([RISCV_ENABLE_ICSIM],,[Define if instruction cache simulator is enabled])
+])
+
 libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a
 AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"])