[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / riscv.ac

diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index e6866c75dc16903f048c4b5b493ed840abf4a573..00358fdbe098350f61616ea51b8ad92140c0df75 100644 (file)
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -1,3 +1,28 @@
+AC_ARG_ENABLE([fpu], AS_HELP_STRING([--disable-fpu], [Disable floating-point]))
+AS_IF([test "x$enable_fpu" != "xno"], [
+  AC_DEFINE([RISCV_ENABLE_FPU],,[Define if floating-point instructions are supported])
+])
+
+AC_ARG_ENABLE([64bit], AS_HELP_STRING([--disable-64bit], [Disable 64-bit mode]))
+AS_IF([test "x$enable_64bit" != "xno"], [
+  AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported])
+])
+
+AC_ARG_ENABLE([rvc], AS_HELP_STRING([--enable-rvc], [Enable instruction compression]))
+AS_IF([test "x$enable_rvc" = "xyes"], [
+  AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported])
+])
+
+AC_ARG_ENABLE([vec], AS_HELP_STRING([--disable-vec], [Disable vector processor]))
+AS_IF([test "x$enable_vec" != "xno"], [
+  AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported])
+])
+
+AC_ARG_ENABLE([icsim], AS_HELP_STRING([--enable-icsim], [Enable instruction cache simulator]))
+AS_IF([test "x$enable_icsim" = "xyes"], [
+  AC_DEFINE([RISCV_ENABLE_ICSIM],,[Define if instruction cache simulator is enabled])
+])
+
 libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a
 AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"])