Implement RVC draft

[riscv-isa-sim.git] / riscv / riscv.ac

diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index d38a48cdecafd10e745a24fbe989d989ccd4d7f5..0b095e857f83a0e0ff73d6c221c1dd1b6ce3b605 100644 (file)
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -1,3 +1,5 @@
+AC_LANG_CPLUSPLUS
+
 AC_ARG_WITH([fesvr],
   [AS_HELP_STRING([--with-fesvr],
     [path to your fesvr installation if not in a standard location])],
@@ -16,6 +18,11 @@ AS_IF([test "x$enable_fpu" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_FPU],,[Define if floating-point instructions are supported])
 ])
 
+AC_ARG_ENABLE([rvc], AS_HELP_STRING([--disable-rvc], [Disable RISC-V Compressed]))
+AS_IF([test "x$enable_rvc" != "xno"], [
+  AC_DEFINE([RISCV_ENABLE_RVC],,[Define if RISC-V Compressed is supported])
+])
+
 AC_ARG_ENABLE([64bit], AS_HELP_STRING([--disable-64bit], [Disable 64-bit mode]))
 AS_IF([test "x$enable_64bit" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported])