Add --enable-misaligned option for misaligned ld/st support

[riscv-isa-sim.git] / riscv / riscv.ac

diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 2a8ee539817b0b7c5b22c96ec96a7eaf0e45110d..68bcdb55d17f175ca1c8a52a0d2df768375d475d 100644 (file)
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -1,5 +1,11 @@
 AC_LANG_CPLUSPLUS
 
+AC_ARG_WITH(isa,
+       [AS_HELP_STRING([--with-isa=RV64IMAFDC],
+               [Sets the default RISC-V ISA])],
+  AC_DEFINE_UNQUOTED([DEFAULT_ISA], "$withval", [Default value for --isa switch]),
+  AC_DEFINE_UNQUOTED([DEFAULT_ISA], "RV64IMAFDC", [Default value for --isa switch]))
+
 AC_SEARCH_LIBS([dlopen], [dl dld], [], [
   AC_MSG_ERROR([unable to find the dlopen() function])
 ])
@@ -26,3 +32,13 @@ AC_ARG_ENABLE([histogram], AS_HELP_STRING([--enable-histogram], [Enable PC histo
 AS_IF([test "x$enable_histogram" = "xyes"], [
   AC_DEFINE([RISCV_ENABLE_HISTOGRAM],,[Enable PC histogram generation])
 ])
+
+AC_ARG_ENABLE([dirty], AS_HELP_STRING([--enable-dirty], [Enable hardware management of PTE accessed and dirty bits]))
+AS_IF([test "x$enable_dirty" = "xyes"], [
+  AC_DEFINE([RISCV_ENABLE_DIRTY],,[Enable hardware management of PTE accessed and dirty bits])
+])
+
+AC_ARG_ENABLE([misaligned], AS_HELP_STRING([--enable-misaligned], [Enable hardware support for misaligned loads and stores]))
+AS_IF([test "x$enable_misaligned" = "xyes"], [
+  AC_DEFINE([RISCV_ENABLE_MISALIGNED],,[Enable hardware support for misaligned loads and stores])
+])