Set tval to 0 on traps with no specified tval

[riscv-isa-sim.git] / riscv / riscv.ac

diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 7b48be64d800bf9b6fd914004909431226e7609c..68bcdb55d17f175ca1c8a52a0d2df768375d475d 100644 (file)
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -32,3 +32,13 @@ AC_ARG_ENABLE([histogram], AS_HELP_STRING([--enable-histogram], [Enable PC histo
 AS_IF([test "x$enable_histogram" = "xyes"], [
   AC_DEFINE([RISCV_ENABLE_HISTOGRAM],,[Enable PC histogram generation])
 ])
+
+AC_ARG_ENABLE([dirty], AS_HELP_STRING([--enable-dirty], [Enable hardware management of PTE accessed and dirty bits]))
+AS_IF([test "x$enable_dirty" = "xyes"], [
+  AC_DEFINE([RISCV_ENABLE_DIRTY],,[Enable hardware management of PTE accessed and dirty bits])
+])
+
+AC_ARG_ENABLE([misaligned], AS_HELP_STRING([--enable-misaligned], [Enable hardware support for misaligned loads and stores]))
+AS_IF([test "x$enable_misaligned" = "xyes"], [
+  AC_DEFINE([RISCV_ENABLE_MISALIGNED],,[Enable hardware support for misaligned loads and stores])
+])