[sim] added icache simulator (disabled by default)

[riscv-isa-sim.git] / riscv / riscv.ac

diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 36c701a484851cedc8f5b1032b2814944bca0151..897b21fba563dbec25f26685af1b2b2169703920 100644 (file)
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -18,6 +18,11 @@ AS_IF([test "x$enable_vec" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported])
 ])
 
+AC_ARG_ENABLE([icsim], AS_HELP_STRING([--disable-icsim], [Enable instruction cache simulator]))
+AS_IF([test "x$enable_icsim" = "xyes"], [
+  AC_DEFINE([RISCV_ENABLE_ICSIM],,[Define if instruction cache simulator is enabled])
+])
+
 libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a
 AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"])