[sim,opcodes] improved sim build and run performance

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 62d604631ef5a40593a32585b88b49ad3233ffa9..202d437054f109f999e19596fad58e11c1b6b898 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -3,10 +3,10 @@ riscv_subproject_deps = \
        softfloat \
 
 riscv_hdrs = \
-    applink.h \
+       applink.h \
        common.h \
        decode.h \
-       execute.h \
+       dispatch.h \
        mmu.h \
        processor.h \
        sim.h \
@@ -14,12 +14,22 @@ riscv_hdrs = \
        insns/*.h \
 
 riscv_srcs = \
-    applink.cc \
+       applink.cc \
        processor.cc \
        sim.cc \
        trap.cc \
        icsim.cc \
        mmu.cc \
+       dispatch_0.cc \
+       dispatch_1.cc \
+       dispatch_2.cc \
+       dispatch_3.cc \
+       dispatch_4.cc \
+       dispatch_5.cc \
+       dispatch_6.cc \
+       dispatch_7.cc \
+       dispatch_8.cc \
+       dispatch_9.cc \
 
 riscv_test_srcs =