FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 18d91c569433d2543f34724c4f342f6f0c3cd535..5508a292785d2c62795d61ca989d0a4d457bcddf 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -7,7 +7,6 @@ riscv_subproject_deps = \
 riscv_install_prog_srcs = \
 
 riscv_hdrs = \
-       htif.h \
        common.h \
        decode.h \
        devices.h \
@@ -24,12 +23,13 @@ riscv_hdrs = \
        rocc.h \
        insn_template.h \
        mulhi.h \
+       gdbserver.h \
+       debug_module.h \
 
 riscv_precompiled_hdrs = \
        insn_template.h \
 
 riscv_srcs = \
-       htif.cc \
        processor.cc \
        execute.cc \
        sim.cc \
@@ -44,7 +44,9 @@ riscv_srcs = \
        regnames.cc \
        devices.cc \
        rom.cc \
-       rtc.cc \
+       clint.cc \
+       gdbserver.cc \
+       debug_module.cc \
        $(riscv_gen_srcs) \
 
 riscv_test_srcs =
@@ -130,6 +132,7 @@ riscv_insn_list = \
        divu \
        divuw \
        divw \
+       dret \
        ebreak \
        ecall \
        fadd_d \
@@ -177,9 +180,9 @@ riscv_insn_list = \
        fmul_d \
        fmul_s \
        fmv_d_x \
-       fmv_s_x \
+       fmv_w_x \
        fmv_x_d \
-       fmv_x_s \
+       fmv_x_w \
        fnmadd_d \
        fnmadd_s \
        fnmsub_d \
@@ -224,7 +227,7 @@ riscv_insn_list = \
        sc_d \
        sc_w \
        sd \
-       sfence_vm \
+       sfence_vma \
        sh \
        sll \
        slli \