FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 1d9b301344b7a190979800879353c1e1eac4753f..5508a292785d2c62795d61ca989d0a4d457bcddf 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -7,9 +7,9 @@ riscv_subproject_deps = \
 riscv_install_prog_srcs = \
 
 riscv_hdrs = \
-       htif.h \
        common.h \
        decode.h \
+       devices.h \
        disasm.h \
        mmu.h \
        processor.h \
@@ -18,16 +18,18 @@ riscv_hdrs = \
        encoding.h \
        cachesim.h \
        memtracer.h \
+       tracer.h \
        extension.h \
        rocc.h \
        insn_template.h \
        mulhi.h \
+       gdbserver.h \
+       debug_module.h \
 
 riscv_precompiled_hdrs = \
        insn_template.h \
 
 riscv_srcs = \
-       htif.cc \
        processor.cc \
        execute.cc \
        sim.cc \
@@ -41,6 +43,10 @@ riscv_srcs = \
        rocc.cc \
        regnames.cc \
        devices.cc \
+       rom.cc \
+       clint.cc \
+       gdbserver.cc \
+       debug_module.cc \
        $(riscv_gen_srcs) \
 
 riscv_test_srcs =
@@ -126,6 +132,9 @@ riscv_insn_list = \
        divu \
        divuw \
        divw \
+       dret \
+       ebreak \
+       ecall \
        fadd_d \
        fadd_s \
        fclass_d \
@@ -171,9 +180,9 @@ riscv_insn_list = \
        fmul_d \
        fmul_s \
        fmv_d_x \
-       fmv_s_x \
+       fmv_w_x \
        fmv_x_d \
-       fmv_x_s \
+       fmv_x_w \
        fnmadd_d \
        fnmadd_s \
        fnmsub_d \
@@ -202,6 +211,7 @@ riscv_insn_list = \
        lui \
        lw \
        lwu \
+       mret \
        mul \
        mulh \
        mulhsu \
@@ -214,12 +224,10 @@ riscv_insn_list = \
        remuw \
        remw \
        sb \
-       sbreak \
-       scall \
        sc_d \
        sc_w \
        sd \
-       sfence_vm \
+       sfence_vma \
        sh \
        sll \
        slli \