Implement RoCC and add a dummy RoCC

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index b9030dbad5cf73c6eaa214fe2028379a31c417c8..781a1a33c0f7078d1868981e6634c67d3a1c009a 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -21,6 +21,9 @@ riscv_hdrs = \
        opcodes.h \
        cachesim.h \
        memtracer.h \
+       extension.h \
+       rocc.h \
+       dummy-rocc.h \
 
 riscv_srcs = \
        htif.cc \
@@ -31,6 +34,8 @@ riscv_srcs = \
        cachesim.cc \
        mmu.cc \
        disasm.cc \
+  extension.cc \
+  rocc.cc \
        $(riscv_gen_srcs) \
 
 riscv_test_srcs =