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Fix 2 trigger corner cases. (#229)
[riscv-isa-sim.git]
/
riscv
/
riscv.mk.in
diff --git
a/riscv/riscv.mk.in
b/riscv/riscv.mk.in
index 233953f1ecd53286b729e6d671ef3db757c70c80..80755e711c181794e3ea9cb96ea40443d06e1d2b 100644
(file)
--- a/
riscv/riscv.mk.in
+++ b/
riscv/riscv.mk.in
@@
-15,6
+15,7
@@
riscv_hdrs = \
mmu.h \
processor.h \
sim.h \
+ simif.h \
trap.h \
encoding.h \
cachesim.h \
@@
-25,6
+26,7
@@
riscv_hdrs = \
insn_template.h \
mulhi.h \
debug_module.h \
+ debug_rom_defines.h \
remote_bitbang.h \
jtag_dtm.h \