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[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 757b3f091b8cb07cf6e1f983ee053b3952b08f5b..c7d84f794559b48dc7ab76c5b2a93b909f3966b4 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -11,7 +11,6 @@ riscv_hdrs = \
        common.h \
        decode.h \
        devices.h \
-       devicetree.h \
        disasm.h \
        mmu.h \
        processor.h \
@@ -25,6 +24,7 @@ riscv_hdrs = \
        rocc.h \
        insn_template.h \
        mulhi.h \
+       gdbserver.h \
 
 riscv_precompiled_hdrs = \
        insn_template.h \
@@ -46,6 +46,7 @@ riscv_srcs = \
        devices.cc \
        rom.cc \
        rtc.cc \
+       gdbserver.cc \
        $(riscv_gen_srcs) \
 
 riscv_test_srcs =