Support setting ISA/subsets with --isa flag

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 45c5ee7acc73c5ae8732890a2caae9ce9bee200e..d30725935583f929c8a0017b3dfecf7feb4f3e5b 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -2,15 +2,9 @@ get_insn_list = $(shell grep ^DECLARE_INSN $(1) | sed 's/DECLARE_INSN(\(.*\),.*,
 get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
 
 riscv_subproject_deps = \
-       softfloat_riscv \
        softfloat \
-       hwacha \
 
 riscv_install_prog_srcs = \
-       spike.cc \
-       riscv-dis.cc \
-       xspike.cc \
-       termios-xspike.cc \
 
 riscv_hdrs = \
        htif.h \
@@ -25,7 +19,11 @@ riscv_hdrs = \
        memtracer.h \
        extension.h \
        rocc.h \
-       dummy-rocc.h \
+       insn_template.h \
+       mulhi.h \
+
+riscv_precompiled_hdrs = \
+       insn_template.h \
 
 riscv_srcs = \
        htif.cc \
@@ -36,20 +34,25 @@ riscv_srcs = \
        cachesim.cc \
        mmu.cc \
        disasm.cc \
-  extension.cc \
-  rocc.cc \
+       extension.cc \
+       extensions.cc \
+       rocc.cc \
+       regnames.cc \
        $(riscv_gen_srcs) \
 
 riscv_test_srcs =
 
 riscv_gen_hdrs = \
-  icache.h \
+       icache.h \
 
 riscv_gen_srcs = \
        $(addsuffix .cc, $(call get_insn_list,$(src_dir)/riscv/encoding.h))
 
-icache.h:
-       $(src_dir)/riscv/gen_icache 1024 > $@
+icache_entries := `grep "ICACHE_ENTRIES =" $(src_dir)/riscv/mmu.h | sed 's/.* = \(.*\);/\1/'`
+
+icache.h: mmu.h
+       $(src_dir)/riscv/gen_icache $(icache_entries) > $@.tmp
+       mv $@.tmp $@
 
 $(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc
        sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@