[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 54fc380c20229a7ab20248707a48489497db625c..f075f47c493af6e6ec79ffa2d754c4136132d75d 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -1,23 +1,58 @@
-riscv_subproject_deps =
+riscv_subproject_deps = \
+       softfloat_riscv \
+       softfloat \
+
+riscv_insn_hdrs := $(notdir $(wildcard $(src_dir)/riscv/insns/*.h))
 
 riscv_hdrs = \
-    applink.h \
+       applink.h \
        common.h \
        decode.h \
-       execute.h \
-       load_elf.h \
        mmu.h \
        processor.h \
        sim.h \
        trap.h \
-       insns/*.h \
+       opcodes.h \
+       insn_header.h \
+       insn_footer.h \
+       dispatch.h \
+
+NDISPATCH := 10
+DISPATCH_SRCS := \
+       dispatch0.cc \
+       dispatch1.cc \
+       dispatch2.cc \
+       dispatch3.cc \
+       dispatch4.cc \
+       dispatch5.cc \
+       dispatch6.cc \
+       dispatch7.cc \
+       dispatch8.cc \
+       dispatch9.cc \
+       dispatch10.cc \
+
+$(DISPATCH_SRCS): %.cc: dispatch $(wildcard insns/*.h) $(riscv_hdrs)
+       $< $(subst dispatch,,$(subst .cc,,$@)) $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
+
+$(src_dir)/riscv/dispatch.h: %.h: dispatch
+       $< $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
+
+$(patsubst %.h, %.cc, $(riscv_insn_hdrs)): %.cc: insns/%.h $(riscv_hdrs)
+       @echo \#define FUNC insn_func_$(@:.cc=)      > $@
+       @echo \#define OPCODE_MASK MASK_$(@:.cc=)   >> $@
+       @echo \#define OPCODE_MATCH MATCH_$(@:.cc=) >> $@
+       @cat $(src_dir)/riscv/insn_header.h         >> $@
+       @cat $<                                     >> $@
+       @cat $(src_dir)/riscv/insn_footer.h         >> $@
 
 riscv_srcs = \
-    applink.cc \
-       load_elf.cc \
+       applink.cc \
        processor.cc \
        sim.cc \
        trap.cc \
+       icsim.cc \
+       mmu.cc \
+       $(DISPATCH_SRCS) \
 
 riscv_test_srcs =