Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / rocc.cc

diff --git a/riscv/rocc.cc b/riscv/rocc.cc
index 3e8596f0c11ad7b33e46c695e2286a0fc9a45b11..a4766d4c8d41e628429017f2aee4c5817bde0b8d 100644 (file)
--- a/riscv/rocc.cc
+++ b/riscv/rocc.cc
@@ -18,7 +18,7 @@ union rocc_insn_union_t
     reg_t xs2 = u.r.xs1 ? RS2 : -1; \
     reg_t xd = rocc->custom##n(u.r, xs1, xs2); \
     if (u.r.xd) \
-      RD = xd; \
+      WRITE_RD(xd); \
     return pc+4; \
   } \
   \