Set tval to 0 on traps with no specified tval

[riscv-isa-sim.git] / riscv / rocc.cc

diff --git a/riscv/rocc.cc b/riscv/rocc.cc
index b14831939e1f50ff21405c90e0c83d852ca0238e..db03e37c4869e39f5a96808706dac09a3e25b266 100644 (file)
--- a/riscv/rocc.cc
+++ b/riscv/rocc.cc
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #include "rocc.h"
 #include "trap.h"
 #include <cstdlib>
@@ -36,3 +38,9 @@ std::vector<insn_desc_t> rocc_t::get_instructions()
   insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3});
   return insns;
 }
+
+std::vector<disasm_insn_t*> rocc_t::get_disasms()
+{
+  std::vector<disasm_insn_t*> insns;
+  return insns;
+}