Merge pull request #117 from riscv/multicore_debug

[riscv-isa-sim.git] / riscv / rocc.cc

diff --git a/riscv/rocc.cc b/riscv/rocc.cc
index 3e8596f0c11ad7b33e46c695e2286a0fc9a45b11..db03e37c4869e39f5a96808706dac09a3e25b266 100644 (file)
--- a/riscv/rocc.cc
+++ b/riscv/rocc.cc
@@ -1,13 +1,9 @@
+// See LICENSE for license details.
+
 #include "rocc.h"
 #include "trap.h"
 #include <cstdlib>
 
-union rocc_insn_union_t
-{
-  rocc_insn_t r;
-  insn_t i;
-};
-
 #define customX(n) \
   static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \
   { \
@@ -15,10 +11,10 @@ union rocc_insn_union_t
     rocc_insn_union_t u; \
     u.i = insn; \
     reg_t xs1 = u.r.xs1 ? RS1 : -1; \
-    reg_t xs2 = u.r.xs1 ? RS2 : -1; \
+    reg_t xs2 = u.r.xs2 ? RS2 : -1; \
     reg_t xd = rocc->custom##n(u.r, xs1, xs2); \
     if (u.r.xd) \
-      RD = xd; \
+      WRITE_RD(xd); \
     return pc+4; \
   } \
   \
@@ -37,8 +33,14 @@ std::vector<insn_desc_t> rocc_t::get_instructions()
 {
   std::vector<insn_desc_t> insns;
   insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0});
-  insns.push_back((insn_desc_t){0x0f, 0x7f, &::illegal_instruction, c1});
+  insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, c1});
   insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2});
   insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3});
   return insns;
 }
+
+std::vector<disasm_insn_t*> rocc_t::get_disasms()
+{
+  std::vector<disasm_insn_t*> insns;
+  return insns;
+}