Add -H to start halted.

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 0fdd8297f421f03220ed75d2c4fce1b4dd0a85e5..09c8b4402455acd9b89ef3279b60d54d66aee274 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -1,9 +1,11 @@
 // See LICENSE for license details.
 
 #include "sim.h"
+#include "mmu.h"
 #include "htif.h"
 #include <map>
 #include <iostream>
+#include <sstream>
 #include <climits>
 #include <cstdlib>
 #include <cassert>
@@ -18,7 +20,7 @@ static void handle_signal(int sig)
   signal(sig, &handle_signal);
 }
 
-sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
+sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
              const std::vector<std::string>& args)
   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
     current_step(0), current_proc(0), debug(false)
@@ -29,20 +31,25 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
   size_t memsz0 = (size_t)mem_mb << 20;
   size_t quantum = 1L << 20;
   if (memsz0 == 0)
-    memsz0 = 1L << (sizeof(size_t) == 8 ? 32 : 30);
+    memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
 
   memsz = memsz0;
   while ((mem = (char*)calloc(1, memsz)) == NULL)
-    memsz = memsz*10/11/quantum*quantum;
+    memsz = (size_t)(memsz*0.9)/quantum*quantum;
 
   if (memsz != memsz0)
     fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
             (unsigned long)memsz, (unsigned long)memsz0);
 
-  debug_mmu = new mmu_t(mem, memsz);
+  debug_mmu = new mmu_t(this, NULL);
 
-  for (size_t i = 0; i < procs.size(); i++)
+  for (size_t i = 0; i < procs.size(); i++) {
     procs[i] = new processor_t(isa, this, i);
+    procs[i]->set_halted(halted);
+  }
+
+  rtc.reset(new rtc_t(procs));
+  make_config_string();
 }
 
 sim_t::~sim_t()
@@ -53,30 +60,19 @@ sim_t::~sim_t()
   free(mem);
 }
 
-void sim_t::send_ipi(reg_t who)
-{
-  if (who < procs.size())
-    procs[who]->deliver_ipi();
-}
-
-reg_t sim_t::get_scr(int which)
-{
-  switch (which)
-  {
-    case 0: return procs.size();
-    case 1: return memsz >> 20;
-    default: return -1;
-  }
-}
-
 int sim_t::run()
 {
+  if (!debug && log)
+    set_procs_debug(true);
   while (htif->tick())
   {
     if (debug || ctrlc_pressed)
       interactive();
     else
       step(INTERLEAVE);
+    if (gdbserver) {
+        gdbserver->handle();
+    }
   }
   return htif->exit_code();
 }
@@ -93,8 +89,10 @@ void sim_t::step(size_t n)
     {
       current_step = 0;
       procs[current_proc]->yield_load_reservation();
-      if (++current_proc == procs.size())
+      if (++current_proc == procs.size()) {
         current_proc = 0;
+        rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
+      }
 
       htif->tick();
     }
@@ -109,16 +107,14 @@ bool sim_t::running()
   return false;
 }
 
-void sim_t::stop()
+void sim_t::set_debug(bool value)
 {
-  procs[0]->state.tohost = 1;
-  while (htif->tick())
-    ;
+  debug = value;
 }
 
-void sim_t::set_debug(bool value)
+void sim_t::set_log(bool value)
 {
-  debug = value;
+  log = value;
 }
 
 void sim_t::set_histogram(bool value)
@@ -135,3 +131,74 @@ void sim_t::set_procs_debug(bool value)
     procs[i]->set_debug(value);
 }
 
+bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
+{
+  if (addr + len < addr)
+    return false;
+  return bus.load(addr, len, bytes);
+}
+
+bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
+{
+  if (addr + len < addr)
+    return false;
+  return bus.store(addr, len, bytes);
+}
+
+void sim_t::make_config_string()
+{
+  reg_t rtc_addr = EXT_IO_BASE;
+  bus.add_device(rtc_addr, rtc.get());
+
+  const int align = 0x1000;
+  reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
+  reg_t cpu_size = align;
+
+  uint32_t reset_vec[8] = {
+    0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
+    0x00028067,                         //   jump straight to DRAM_BASE
+    0x00000000,                         // reserved
+    0,                                  // config string pointer
+    0, 0, 0, 0                          // trap vector
+  };
+  reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer
+
+  std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
+
+  std::stringstream s;
+  s << std::hex <<
+        "platform {\n"
+        "  vendor ucb;\n"
+        "  arch spike;\n"
+        "};\n"
+        "rtc {\n"
+        "  addr 0x" << rtc_addr << ";\n"
+        "};\n"
+        "ram {\n"
+        "  0 {\n"
+        "    addr 0x" << DRAM_BASE << ";\n"
+        "    size 0x" << memsz << ";\n"
+        "  };\n"
+        "};\n"
+        "core {\n";
+  for (size_t i = 0; i < procs.size(); i++) {
+    s <<
+        "  " << i << " {\n"
+        "    " << "0 {\n" << // hart 0 on core i
+        "      isa " << procs[i]->isa_string << ";\n"
+        "      timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n"
+        "      ipi 0x" << cpu_addr << ";\n"
+        "    };\n"
+        "  };\n";
+    bus.add_device(cpu_addr, procs[i]);
+    cpu_addr += cpu_size;
+  }
+  s <<  "};\n";
+
+  config_string = s.str();
+  rom.insert(rom.end(), config_string.begin(), config_string.end());
+  rom.resize((rom.size() / align + 1) * align);
+
+  boot_rom.reset(new rom_device_t(rom));
+  bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
+}