new supervisor mode

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index fb533a8898d7d3eb830699eef2c9342b1f2f5d2a..0d0b55552678051be19c64092cd7d5aaf9e986f1 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -63,6 +63,11 @@ void sim_t::set_tohost(reg_t val)
   htif->wait_for_tohost_write();
 }
 
+reg_t sim_t::get_tohost()
+{
+  return tohost;
+}
+
 reg_t sim_t::get_fromhost()
 {
   htif->wait_for_fromhost_write();