#include "sim.h"
#include "mmu.h"
-#include "gdbserver.h"
+#include "remote_bitbang.h"
#include <map>
#include <iostream>
#include <sstream>
signal(sig, &handle_signal);
}
-sim_t::sim_t(const char* isa, size_t nprocs, bool halted,
+sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
std::vector<std::pair<reg_t, mem_t*>> mems,
- const std::vector<std::string>& args)
+ const std::vector<std::string>& args,
+ std::vector<int> const hartids, unsigned progsize,
+ unsigned max_bus_master_bits, bool require_authentication)
: htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))),
- current_step(0), current_proc(0), debug(false), gdbserver(NULL)
+ start_pc(start_pc), current_step(0), current_proc(0), debug(false),
+ remote_bitbang(NULL),
+ debug_module(this, progsize, max_bus_master_bits, require_authentication)
{
signal(SIGINT, &handle_signal);
for (auto& x : mems)
bus.add_device(x.first, x.second);
- bus.add_device(DEBUG_START, &debug_module);
+ debug_module.add_device(&bus);
debug_mmu = new mmu_t(this, NULL);
- for (size_t i = 0; i < procs.size(); i++) {
- procs[i] = new processor_t(isa, this, i, halted);
+ if (hartids.size() == 0) {
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i] = new processor_t(isa, this, i, halted);
+ }
+ }
+ else {
+ if (hartids.size() != procs.size()) {
+ std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl;
+ exit(1);
+ }
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i] = new processor_t(isa, this, hartids[i], halted);
+ }
}
clint.reset(new clint_t(procs));
bus.add_device(CLINT_BASE, clint.get());
-
- make_dtb();
}
sim_t::~sim_t()
interactive();
else
step(INTERLEAVE);
- if (gdbserver) {
- gdbserver->handle();
+ if (remote_bitbang) {
+ remote_bitbang->tick();
}
}
}
void sim_t::make_dtb()
{
- uint32_t reset_vec[] = {
- 0x297 + DRAM_BASE - DEFAULT_RSTVEC, // auipc t0, DRAM_BASE
- 0x597, // auipc a1, 0
- 0x58593, // addi a1, a1, 0
- 0xf1402573, // csrr a0,mhartid
- 0x00028067 // jalr zero, t0, 0 (jump straight to DRAM_BASE)
+ const int reset_vec_size = 8;
+
+ start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc;
+
+ uint32_t reset_vec[reset_vec_size] = {
+ 0x297, // auipc t0,0x0
+ 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb
+ 0xf1402573, // csrr a0, mhartid
+ get_core(0)->xlen == 32 ?
+ 0x0182a283u : // lw t0,24(t0)
+ 0x0182b283u, // ld t0,24(t0)
+ 0x28067, // jr t0
+ 0,
+ (uint32_t) (start_pc & 0xffffffff),
+ (uint32_t) (start_pc >> 32)
};
- reset_vec[2] += (sizeof(reset_vec) - 4) << 20; // addi a1, a1, sizeof(reset_vec) - 4 = DTB start
std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
" 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
" };\n"
" };\n"
+ " htif {\n"
+ " compatible = \"ucb,htif0\";\n"
+ " };\n"
"};\n";
dts = s.str();
char* sim_t::addr_to_mem(reg_t addr) {
auto desc = bus.find_device(addr);
- if (auto mem = dynamic_cast<mem_t*>(desc.device))
- return mem->contents() + (addr - desc.base);
+ if (auto mem = dynamic_cast<mem_t*>(desc.second))
+ if (addr - desc.first < mem->size())
+ return mem->contents() + (addr - desc.first);
return NULL;
}
// htif
+void sim_t::reset()
+{
+ make_dtb();
+}
+
void sim_t::idle()
{
target.switch_to();