// See LICENSE for license details.
#include "sim.h"
-#include "htif.h"
+#include "mmu.h"
+#include "dts.h"
+#include "remote_bitbang.h"
#include <map>
#include <iostream>
+#include <sstream>
#include <climits>
#include <cstdlib>
#include <cassert>
#include <signal.h>
+#include <unistd.h>
+#include <sys/wait.h>
+#include <sys/types.h>
volatile bool ctrlc_pressed = false;
static void handle_signal(int sig)
signal(sig, &handle_signal);
}
-sim_t::sim_t(size_t nprocs, size_t mem_mb, const std::vector<std::string>& args)
- : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
- current_step(0), current_proc(0), debug(false)
+sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
+ std::vector<std::pair<reg_t, mem_t*>> mems,
+ const std::vector<std::string>& args,
+ std::vector<int> const hartids, unsigned progsize,
+ unsigned max_bus_master_bits, bool require_authentication)
+ : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))),
+ start_pc(start_pc), current_step(0), current_proc(0), debug(false),
+ histogram_enabled(false), dtb_enabled(true), remote_bitbang(NULL),
+ debug_module(this, progsize, max_bus_master_bits, require_authentication)
{
signal(SIGINT, &handle_signal);
- // allocate target machine's memory, shrinking it as necessary
- // until the allocation succeeds
- size_t memsz0 = (size_t)mem_mb << 20;
- size_t quantum = 1L << 20;
- if (memsz0 == 0)
- memsz0 = 1L << (sizeof(size_t) == 8 ? 32 : 30);
- memsz = memsz0;
- while ((mem = (char*)calloc(1, memsz)) == NULL)
- memsz = memsz*10/11/quantum*quantum;
+ for (auto& x : mems)
+ bus.add_device(x.first, x.second);
- if (memsz != memsz)
- fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
- (unsigned long)memsz, (unsigned long)memsz0);
+ debug_module.add_device(&bus);
- debug_mmu = new mmu_t(mem, memsz);
+ debug_mmu = new mmu_t(this, NULL);
- for (size_t i = 0; i < procs.size(); i++)
- procs[i] = new processor_t(this, new mmu_t(mem, memsz), i);
+ if (hartids.size() == 0) {
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i] = new processor_t(isa, this, i, halted);
+ }
+ }
+ else {
+ if (hartids.size() != procs.size()) {
+ std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl;
+ exit(1);
+ }
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i] = new processor_t(isa, this, hartids[i], halted);
+ }
+ }
+
+ clint.reset(new clint_t(procs));
+ bus.add_device(CLINT_BASE, clint.get());
}
sim_t::~sim_t()
{
for (size_t i = 0; i < procs.size(); i++)
- {
- mmu_t* pmmu = procs[i]->get_mmu();
delete procs[i];
- delete pmmu;
- }
delete debug_mmu;
- free(mem);
}
-void sim_t::send_ipi(reg_t who)
+void sim_thread_main(void* arg)
{
- if (who < procs.size())
- procs[who]->deliver_ipi();
+ ((sim_t*)arg)->main();
}
-reg_t sim_t::get_scr(int which)
+void sim_t::main()
{
- switch (which)
- {
- case 0: return procs.size();
- case 1: return memsz >> 20;
- default: return -1;
- }
-}
+ if (!debug && log)
+ set_procs_debug(true);
-void sim_t::run()
-{
- while (htif->tick())
+ while (!done())
{
if (debug || ctrlc_pressed)
interactive();
else
- step(INTERLEAVE, false);
+ step(INTERLEAVE);
+ if (remote_bitbang) {
+ remote_bitbang->tick();
+ }
}
}
-void sim_t::step(size_t n, bool noisy)
+int sim_t::run()
+{
+ host = context_t::current();
+ target.init(sim_thread_main, this);
+ return htif_t::run();
+}
+
+void sim_t::step(size_t n)
{
for (size_t i = 0, steps = 0; i < n; i += steps)
{
steps = std::min(n - i, INTERLEAVE - current_step);
- procs[current_proc]->step(steps, noisy);
+ procs[current_proc]->step(steps);
current_step += steps;
if (current_step == INTERLEAVE)
{
current_step = 0;
- procs[current_proc]->yield_load_reservation();
- if (++current_proc == procs.size())
+ procs[current_proc]->get_mmu()->yield_load_reservation();
+ if (++current_proc == procs.size()) {
current_proc = 0;
+ clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
+ }
- htif->tick();
+ host->switch_to();
}
}
}
-bool sim_t::running()
+void sim_t::set_debug(bool value)
{
- for (size_t i = 0; i < procs.size(); i++)
- if (procs[i]->running())
- return true;
- return false;
+ debug = value;
+}
+
+void sim_t::set_log(bool value)
+{
+ log = value;
+}
+
+void sim_t::set_histogram(bool value)
+{
+ histogram_enabled = value;
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i]->set_histogram(histogram_enabled);
+ }
+}
+
+void sim_t::set_procs_debug(bool value)
+{
+ for (size_t i=0; i< procs.size(); i++)
+ procs[i]->set_debug(value);
+}
+
+bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
+{
+ if (addr + len < addr)
+ return false;
+ return bus.load(addr, len, bytes);
+}
+
+bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
+{
+ if (addr + len < addr)
+ return false;
+ return bus.store(addr, len, bytes);
+}
+
+void sim_t::make_dtb()
+{
+ const int reset_vec_size = 8;
+
+ start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc;
+
+ uint32_t reset_vec[reset_vec_size] = {
+ 0x297, // auipc t0,0x0
+ 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb
+ 0xf1402573, // csrr a0, mhartid
+ get_core(0)->get_xlen() == 32 ?
+ 0x0182a283u : // lw t0,24(t0)
+ 0x0182b283u, // ld t0,24(t0)
+ 0x28067, // jr t0
+ 0,
+ (uint32_t) (start_pc & 0xffffffff),
+ (uint32_t) (start_pc >> 32)
+ };
+
+ std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
+
+ dts = make_dts(INSNS_PER_RTC_TICK, CPU_HZ, procs, mems);
+ std::string dtb = dts_compile(dts);
+
+ rom.insert(rom.end(), dtb.begin(), dtb.end());
+ const int align = 0x1000;
+ rom.resize((rom.size() + align - 1) / align * align);
+
+ boot_rom.reset(new rom_device_t(rom));
+ bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
+}
+
+char* sim_t::addr_to_mem(reg_t addr) {
+ auto desc = bus.find_device(addr);
+ if (auto mem = dynamic_cast<mem_t*>(desc.second))
+ if (addr - desc.first < mem->size())
+ return mem->contents() + (addr - desc.first);
+ return NULL;
+}
+
+// htif
+
+void sim_t::reset()
+{
+ if (dtb_enabled)
+ make_dtb();
+}
+
+void sim_t::idle()
+{
+ target.switch_to();
+}
+
+void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
+{
+ assert(len == 8);
+ auto data = debug_mmu->load_uint64(taddr);
+ memcpy(dst, &data, sizeof data);
+}
+
+void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
+{
+ assert(len == 8);
+ uint64_t data;
+ memcpy(&data, src, sizeof data);
+ debug_mmu->store_uint64(taddr, data);
}
-void sim_t::stop()
+void sim_t::proc_reset(unsigned id)
{
- procs[0]->state.tohost = 1;
- while (htif->tick())
- ;
+ debug_module.proc_reset(id);
}
projects / riscv-isa-sim.git / blobdiff