#include "sim.h"
#include "mmu.h"
-#include "htif.h"
+#include "dts.h"
+#include "remote_bitbang.h"
#include <map>
#include <iostream>
#include <sstream>
#include <cstdlib>
#include <cassert>
#include <signal.h>
+#include <unistd.h>
+#include <sys/wait.h>
+#include <sys/types.h>
volatile bool ctrlc_pressed = false;
static void handle_signal(int sig)
signal(sig, &handle_signal);
}
-sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
- const std::vector<std::string>& args)
- : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
- current_step(0), current_proc(0), debug(false)
+sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
+ std::vector<std::pair<reg_t, mem_t*>> mems,
+ const std::vector<std::string>& args,
+ std::vector<int> const hartids, unsigned progsize,
+ unsigned max_bus_master_bits, bool require_authentication)
+ : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))),
+ start_pc(start_pc), current_step(0), current_proc(0), debug(false),
+ histogram_enabled(false), dtb_enabled(true), remote_bitbang(NULL),
+ debug_module(this, progsize, max_bus_master_bits, require_authentication)
{
signal(SIGINT, &handle_signal);
- // allocate target machine's memory, shrinking it as necessary
- // until the allocation succeeds
- size_t memsz0 = (size_t)mem_mb << 20;
- size_t quantum = 1L << 20;
- if (memsz0 == 0)
- memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
- memsz = memsz0;
- while ((mem = (char*)calloc(1, memsz)) == NULL)
- memsz = (size_t)(memsz*0.9)/quantum*quantum;
+ for (auto& x : mems)
+ bus.add_device(x.first, x.second);
- if (memsz != memsz0)
- fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
- (unsigned long)memsz, (unsigned long)memsz0);
+ debug_module.add_device(&bus);
debug_mmu = new mmu_t(this, NULL);
- for (size_t i = 0; i < procs.size(); i++)
- procs[i] = new processor_t(isa, this, i);
+ if (hartids.size() == 0) {
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i] = new processor_t(isa, this, i, halted);
+ }
+ }
+ else {
+ if (hartids.size() != procs.size()) {
+ std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl;
+ exit(1);
+ }
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i] = new processor_t(isa, this, hartids[i], halted);
+ }
+ }
- rtc.reset(new rtc_t(procs));
- make_config_string();
+ clint.reset(new clint_t(procs));
+ bus.add_device(CLINT_BASE, clint.get());
}
sim_t::~sim_t()
for (size_t i = 0; i < procs.size(); i++)
delete procs[i];
delete debug_mmu;
- free(mem);
}
-int sim_t::run()
+void sim_thread_main(void* arg)
+{
+ ((sim_t*)arg)->main();
+}
+
+void sim_t::main()
{
if (!debug && log)
set_procs_debug(true);
- while (htif->tick())
+
+ while (!done())
{
if (debug || ctrlc_pressed)
interactive();
else
step(INTERLEAVE);
+ if (remote_bitbang) {
+ remote_bitbang->tick();
+ }
}
- return htif->exit_code();
+}
+
+int sim_t::run()
+{
+ host = context_t::current();
+ target.init(sim_thread_main, this);
+ return htif_t::run();
}
void sim_t::step(size_t n)
if (current_step == INTERLEAVE)
{
current_step = 0;
- procs[current_proc]->yield_load_reservation();
+ procs[current_proc]->get_mmu()->yield_load_reservation();
if (++current_proc == procs.size()) {
current_proc = 0;
- rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
+ clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
}
- htif->tick();
+ host->switch_to();
}
}
}
-bool sim_t::running()
-{
- for (size_t i = 0; i < procs.size(); i++)
- if (procs[i]->running())
- return true;
- return false;
-}
-
void sim_t::set_debug(bool value)
{
debug = value;
return bus.store(addr, len, bytes);
}
-void sim_t::make_config_string()
+void sim_t::make_dtb()
{
- reg_t rtc_addr = EXT_IO_BASE;
- bus.add_device(rtc_addr, rtc.get());
-
- const int align = 0x1000;
- reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
- reg_t cpu_size = align;
-
- uint32_t reset_vec[8] = {
- 0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
- 0x00028067, // jump straight to DRAM_BASE
- 0x00000000, // reserved
- 0, // config string pointer
- 0, 0, 0, 0 // trap vector
+ const int reset_vec_size = 8;
+
+ start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc;
+
+ uint32_t reset_vec[reset_vec_size] = {
+ 0x297, // auipc t0,0x0
+ 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb
+ 0xf1402573, // csrr a0, mhartid
+ get_core(0)->get_xlen() == 32 ?
+ 0x0182a283u : // lw t0,24(t0)
+ 0x0182b283u, // ld t0,24(t0)
+ 0x28067, // jr t0
+ 0,
+ (uint32_t) (start_pc & 0xffffffff),
+ (uint32_t) (start_pc >> 32)
};
- reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer
std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
- std::stringstream s;
- s << std::hex <<
- "platform {\n"
- " vendor ucb;\n"
- " arch spike;\n"
- "};\n"
- "rtc {\n"
- " addr 0x" << rtc_addr << ";\n"
- "};\n"
- "ram {\n"
- " 0 {\n"
- " addr 0x" << DRAM_BASE << ";\n"
- " size 0x" << memsz << ";\n"
- " };\n"
- "};\n"
- "core {\n";
- for (size_t i = 0; i < procs.size(); i++) {
- s <<
- " " << i << " {\n"
- " " << "0 {\n" << // hart 0 on core i
- " isa " << procs[i]->isa_string << ";\n"
- " timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n"
- " ipi 0x" << cpu_addr << ";\n"
- " };\n"
- " };\n";
- bus.add_device(cpu_addr, procs[i]);
- cpu_addr += cpu_size;
- }
- s << "};\n";
+ dts = make_dts(INSNS_PER_RTC_TICK, CPU_HZ, procs, mems);
+ std::string dtb = dts_compile(dts);
- config_string = s.str();
- rom.insert(rom.end(), config_string.begin(), config_string.end());
- rom.resize((rom.size() / align + 1) * align);
+ rom.insert(rom.end(), dtb.begin(), dtb.end());
+ const int align = 0x1000;
+ rom.resize((rom.size() + align - 1) / align * align);
boot_rom.reset(new rom_device_t(rom));
bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
}
+
+char* sim_t::addr_to_mem(reg_t addr) {
+ auto desc = bus.find_device(addr);
+ if (auto mem = dynamic_cast<mem_t*>(desc.second))
+ if (addr - desc.first < mem->size())
+ return mem->contents() + (addr - desc.first);
+ return NULL;
+}
+
+// htif
+
+void sim_t::reset()
+{
+ if (dtb_enabled)
+ make_dtb();
+}
+
+void sim_t::idle()
+{
+ target.switch_to();
+}
+
+void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
+{
+ assert(len == 8);
+ auto data = debug_mmu->load_uint64(taddr);
+ memcpy(dst, &data, sizeof data);
+}
+
+void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
+{
+ assert(len == 8);
+ uint64_t data;
+ memcpy(&data, src, sizeof data);
+ debug_mmu->store_uint64(taddr, data);
+}
+
+void sim_t::proc_reset(unsigned id)
+{
+ debug_module.proc_reset(id);
+}
projects / riscv-isa-sim.git / blobdiff