#include "sim.h"
#include "mmu.h"
-#include "htif.h"
+#include "gdbserver.h"
#include <map>
#include <iostream>
#include <sstream>
#include <cstdlib>
#include <cassert>
#include <signal.h>
+#include <unistd.h>
+#include <sys/wait.h>
+#include <sys/types.h>
volatile bool ctrlc_pressed = false;
static void handle_signal(int sig)
sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
const std::vector<std::string>& args)
- : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
+ : htif_t(args), procs(std::max(nprocs, size_t(1))),
current_step(0), current_proc(0), debug(false), gdbserver(NULL)
{
signal(SIGINT, &handle_signal);
memsz = (size_t)(memsz*0.9)/quantum*quantum;
if (memsz != memsz0)
- fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
- (unsigned long)memsz, (unsigned long)memsz0);
+ fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n",
+ memsz, memsz0);
- /* Copy Debug ROM into the end of the allocated block, because we surely
- * didn't succeed in allocating 0xfffffffff800 bytes. */
- /* TODO: Once everything uses the new memory map, just put this at the
- * address that it actually belongs at. */
- memcpy(mem + memsz - DEBUG_SIZE + DEBUG_ROM_START - DEBUG_START,
- debug_rom_raw, debug_rom_raw_len);
+ bus.add_device(DEBUG_START, &debug_module);
debug_mmu = new mmu_t(this, NULL);
for (size_t i = 0; i < procs.size(); i++) {
- procs[i] = new processor_t(isa, this, i);
- if (halted)
- procs[i]->enter_debug_mode(DCSR_CAUSE_HALT);
+ procs[i] = new processor_t(isa, this, i, halted);
}
rtc.reset(new rtc_t(procs));
- make_config_string();
+ make_dtb();
}
sim_t::~sim_t()
free(mem);
}
-int sim_t::run()
+void sim_thread_main(void* arg)
+{
+ ((sim_t*)arg)->main();
+}
+
+void sim_t::main()
{
if (!debug && log)
set_procs_debug(true);
- while (htif->tick())
+
+ while (!done())
{
if (debug || ctrlc_pressed)
interactive();
else
step(INTERLEAVE);
if (gdbserver) {
- gdbserver->handle();
+ gdbserver->handle();
}
}
- return htif->exit_code();
+}
+
+int sim_t::run()
+{
+ host = context_t::current();
+ target.init(sim_thread_main, this);
+ return htif_t::run();
}
void sim_t::step(size_t n)
rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
}
- htif->tick();
+ host->switch_to();
}
}
}
-bool sim_t::running()
-{
- for (size_t i = 0; i < procs.size(); i++)
- if (procs[i]->running())
- return true;
- return false;
-}
-
void sim_t::set_debug(bool value)
{
debug = value;
return bus.store(addr, len, bytes);
}
-void sim_t::make_config_string()
+static std::string dts_compile(const std::string& dts)
+{
+ // Convert the DTS to DTB
+ int dts_pipe[2];
+ pid_t dts_pid;
+
+ if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) {
+ std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl;
+ exit(1);
+ }
+
+ // Child process to output dts
+ if (dts_pid == 0) {
+ close(dts_pipe[0]);
+ int step, len = dts.length();
+ const char *buf = dts.c_str();
+ for (int done = 0; done < len; done += step) {
+ step = write(dts_pipe[1], buf+done, len-done);
+ if (step == -1) {
+ std::cerr << "Failed to write dts: " << strerror(errno) << std::endl;
+ exit(1);
+ }
+ }
+ close(dts_pipe[1]);
+ exit(0);
+ }
+
+ pid_t dtb_pid;
+ int dtb_pipe[2];
+ if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) {
+ std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl;
+ exit(1);
+ }
+
+ // Child process to output dtb
+ if (dtb_pid == 0) {
+ dup2(dts_pipe[0], 0);
+ dup2(dtb_pipe[1], 1);
+ close(dts_pipe[0]);
+ close(dts_pipe[1]);
+ close(dtb_pipe[0]);
+ close(dtb_pipe[1]);
+ execl(DTC, DTC, "-O", "dtb", 0);
+ std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl;
+ exit(1);
+ }
+
+ close(dts_pipe[1]);
+ close(dts_pipe[0]);
+ close(dtb_pipe[1]);
+
+ // Read-out dtb
+ std::stringstream dtb;
+
+ int got;
+ char buf[4096];
+ while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) {
+ dtb.write(buf, got);
+ }
+ if (got == -1) {
+ std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl;
+ exit(1);
+ }
+ close(dtb_pipe[0]);
+
+ // Reap children
+ int status;
+ waitpid(dts_pid, &status, 0);
+ if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
+ std::cerr << "Child dts process failed" << std::endl;
+ exit(1);
+ }
+ waitpid(dtb_pid, &status, 0);
+ if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
+ std::cerr << "Child dtb process failed" << std::endl;
+ exit(1);
+ }
+
+ return dtb.str();
+}
+
+void sim_t::make_dtb()
{
reg_t rtc_addr = EXT_IO_BASE;
bus.add_device(rtc_addr, rtc.get());
std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
std::stringstream s;
- s << std::hex <<
- "platform {\n"
- " vendor ucb;\n"
- " arch spike;\n"
- "};\n"
- "rtc {\n"
- " addr 0x" << rtc_addr << ";\n"
- "};\n"
- "ram {\n"
- " 0 {\n"
- " addr 0x" << DRAM_BASE << ";\n"
- " size 0x" << memsz << ";\n"
- " };\n"
- "};\n"
- "core {\n";
+ s << std::dec <<
+ "/dts-v1/;\n"
+ "\n"
+ "/ {\n"
+ " #address-cells = <2>;\n"
+ " #size-cells = <2>;\n"
+ " compatible = \"ucbbar,spike-bare-dev\";\n"
+ " model = \"ucbbar,spike-bare\";\n"
+ " cpus {\n"
+ " #address-cells = <1>;\n"
+ " #size-cells = <0>;\n"
+ " timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n";
for (size_t i = 0; i < procs.size(); i++) {
- s <<
- " " << i << " {\n"
- " " << "0 {\n" << // hart 0 on core i
- " isa " << procs[i]->isa_string << ";\n"
- " timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n"
- " ipi 0x" << cpu_addr << ";\n"
- " };\n"
- " };\n";
- bus.add_device(cpu_addr, procs[i]);
- cpu_addr += cpu_size;
+ s << " CPU" << i << ": cpu@" << i << " {\n"
+ " device_type = \"cpu\";\n"
+ " reg = <" << i << ">;\n"
+ " status = \"okay\";\n"
+ " compatible = \"riscv\";\n"
+ " riscv,isa = \"" << procs[i]->isa_string << "\";\n"
+ " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
+ " clock-frequency = <" << CPU_HZ << ">;\n"
+ " };\n";
}
- s << "};\n";
+ reg_t membs = DRAM_BASE;
+ s << std::hex <<
+ " };\n"
+ " memory@" << DRAM_BASE << " {\n"
+ " device_type = \"memory\";\n"
+ " reg = <0x" << (membs >> 32) << " 0x" << (membs & (uint32_t)-1) <<
+ " 0x" << (memsz >> 32) << " 0x" << (memsz & (uint32_t)-1) << ">;\n"
+ " };\n"
+ " soc {\n"
+ " #address-cells = <2>;\n"
+ " #size-cells = <2>;\n"
+ " compatible = \"ucbbar,spike-bare-soc\";\n"
+ " ranges;\n"
+ " clint@" << rtc_addr << " {\n"
+ " compatible = \"riscv,clint0\";\n"
+ " interrupts-extended = <" << std::dec;
+ for (size_t i = 0; i < procs.size(); i++)
+ s << "&CPU" << i << " 3 &CPU" << i << " 7 ";
+ s << std::hex << ">;\n"
+ " reg = <0x" << (rtc_addr >> 32) << " 0x" << (rtc_addr & (uint32_t)-1) <<
+ " 0x0 0x10000>;\n"
+ " };\n"
+ " };\n"
+ "};\n";
+
+ dts = s.str();
+ std::string dtb = dts_compile(dts);
- config_string = s.str();
- rom.insert(rom.end(), config_string.begin(), config_string.end());
+ rom.insert(rom.end(), dtb.begin(), dtb.end());
rom.resize((rom.size() / align + 1) * align);
boot_rom.reset(new rom_device_t(rom));
bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
}
+
+// htif
+
+void sim_t::idle()
+{
+ target.switch_to();
+}
+
+void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
+{
+ assert(len == 8);
+ auto data = debug_mmu->load_uint64(taddr);
+ memcpy(dst, &data, sizeof data);
+}
+
+void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
+{
+ assert(len == 8);
+ uint64_t data;
+ memcpy(&data, src, sizeof data);
+ debug_mmu->store_uint64(taddr, data);
+}
projects / riscv-isa-sim.git / blobdiff