refactor disassembler, and add hwacha disassembler

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index a4a1c172498e1d7bd279bf803c9664582b137c39..4d61555d0b6a8a440812a4ed4ce6453534df6e44 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -79,16 +79,16 @@ void sim_t::run()
     if (debug || ctrlc_pressed)
       interactive();
     else
-      step(INTERLEAVE, false);
+      step(INTERLEAVE);
   }
 }
 
-void sim_t::step(size_t n, bool noisy)
+void sim_t::step(size_t n)
 {
   for (size_t i = 0, steps = 0; i < n; i += steps)
   {
     steps = std::min(n - i, INTERLEAVE - current_step);
-    procs[current_proc]->step(steps, noisy);
+    procs[current_proc]->step(steps);
 
     current_step += steps;
     if (current_step == INTERLEAVE)
@@ -117,3 +117,14 @@ void sim_t::stop()
   while (htif->tick())
     ;
 }
+
+void sim_t::set_debug(bool value)
+{
+  debug = value;
+}
+
+void sim_t::set_procs_debug(bool value)
+{
+  for (size_t i=0; i< procs.size(); i++)
+    procs[i]->set_debug(value);
+}