signal(sig, &handle_signal);
}
-sim_t::sim_t(size_t nprocs, size_t mem_mb, const std::vector<std::string>& args)
+sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
+ const std::vector<std::string>& args)
: htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
- current_step(0), current_proc(0), debug(false)
+ rtc(0), current_step(0), current_proc(0), debug(false)
{
signal(SIGINT, &handle_signal);
// allocate target machine's memory, shrinking it as necessary
debug_mmu = new mmu_t(mem, memsz);
for (size_t i = 0; i < procs.size(); i++)
- procs[i] = new processor_t(this, new mmu_t(mem, memsz), i);
+ procs[i] = new processor_t(isa, this, i);
}
sim_t::~sim_t()
{
for (size_t i = 0; i < procs.size(); i++)
- {
- mmu_t* pmmu = procs[i]->get_mmu();
delete procs[i];
- delete pmmu;
- }
delete debug_mmu;
free(mem);
}
int sim_t::run()
{
+ if (!debug && log)
+ set_procs_debug(true);
while (htif->tick())
{
if (debug || ctrlc_pressed)
{
current_step = 0;
procs[current_proc]->yield_load_reservation();
- if (++current_proc == procs.size())
+ if (++current_proc == procs.size()) {
current_proc = 0;
+ rtc += INTERLEAVE / INSNS_PER_RTC_TICK;
+ }
htif->tick();
}
debug = value;
}
+void sim_t::set_log(bool value)
+{
+ log = value;
+}
+
+void sim_t::set_histogram(bool value)
+{
+ histogram_enabled = value;
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i]->set_histogram(histogram_enabled);
+ }
+}
+
void sim_t::set_procs_debug(bool value)
{
for (size_t i=0; i< procs.size(); i++)
procs[i]->set_debug(value);
}
+