fdt: move interrupt controller into its own node

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 004ccaacd0c1c94e4b2ec89143d3df2811ca30b4..7a10c9b4d2c9a4705cf726c0bd638e242950f7b4 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -34,7 +34,7 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
   size_t memsz0 = (size_t)mem_mb << 20;
   size_t quantum = 1L << 20;
   if (memsz0 == 0)
-    memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
+    memsz0 = (size_t)2048 << 20;
 
   memsz = memsz0;
   while ((mem = (char*)calloc(1, memsz)) == NULL)
@@ -52,8 +52,10 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
     procs[i] = new processor_t(isa, this, i, halted);
   }
 
-  rtc.reset(new rtc_t(procs));
-  make_config_string();
+  clint.reset(new clint_t(procs));
+  bus.add_device(CLINT_BASE, clint.get());
+
+  make_dtb();
 }
 
 sim_t::~sim_t()
@@ -107,7 +109,7 @@ void sim_t::step(size_t n)
       procs[current_proc]->yield_load_reservation();
       if (++current_proc == procs.size()) {
         current_proc = 0;
-        rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
+        clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
       }
 
       host->switch_to();
@@ -234,23 +236,16 @@ static std::string dts_compile(const std::string& dts)
   return dtb.str();
 }
 
-void sim_t::make_config_string()
+void sim_t::make_dtb()
 {
-  reg_t rtc_addr = EXT_IO_BASE;
-  bus.add_device(rtc_addr, rtc.get());
-
-  const int align = 0x1000;
-  reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
-  reg_t cpu_size = align;
-
-  uint32_t reset_vec[8] = {
-    0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
-    0x00028067,                         //   jump straight to DRAM_BASE
-    0x00000000,                         // reserved
-    0,                                  // config string pointer
-    0, 0, 0, 0                          // trap vector
+  uint32_t reset_vec[] = {
+    0x297 + DRAM_BASE - DEFAULT_RSTVEC, // auipc t0, DRAM_BASE
+    0x597,                              // auipc a1, 0
+    0x58593,                            // addi a1, a1, 0
+    0xf1402573,                                // csrr a0,mhartid
+    0x00028067                          // jalr zero, t0, 0 (jump straight to DRAM_BASE)
   };
-  reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer
+  reset_vec[2] += (sizeof(reset_vec) - 4) << 20; // addi a1, a1, sizeof(reset_vec) - 4 = DTB start
 
   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 
@@ -276,6 +271,11 @@ void sim_t::make_config_string()
          "      riscv,isa = \"" << procs[i]->isa_string << "\";\n"
          "      mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
          "      clock-frequency = <" << CPU_HZ << ">;\n"
+         "      CPU" << i << "_intc: interrupt-controller {\n"
+         "        #interrupt-cells = <1>;\n"
+         "        interrupt-controller;\n"
+         "        compatible = \"riscv,cpu-intc\";\n"
+         "      };\n"
          "    };\n";
   }
   reg_t membs = DRAM_BASE;
@@ -289,25 +289,28 @@ void sim_t::make_config_string()
          "  soc {\n"
          "    #address-cells = <2>;\n"
          "    #size-cells = <2>;\n"
-         "    compatible = \"ucbbar,spike-bare-soc\";\n"
+         "    compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
          "    ranges;\n"
-         "    clint@" << rtc_addr << " {\n"
+         "    clint@" << CLINT_BASE << " {\n"
          "      compatible = \"riscv,clint0\";\n"
          "      interrupts-extended = <" << std::dec;
   for (size_t i = 0; i < procs.size(); i++)
-    s << "&CPU" << i << " 3 &CPU" << i << " 7 ";
+    s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 ";
+  reg_t clintbs = CLINT_BASE;
+  reg_t clintsz = CLINT_SIZE;
   s << std::hex << ">;\n"
-         "      reg = <0x" << (rtc_addr >> 32) << " 0x" << (rtc_addr & (uint32_t)-1) <<
-                     " 0x0 0x10000>;\n"
+         "      reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) <<
+                     " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
          "    };\n"
          "  };\n"
          "};\n";
 
-  config_string = s.str();
-  std::string dtb = dts_compile(config_string);
+  dts = s.str();
+  std::string dtb = dts_compile(dts);
 
   rom.insert(rom.end(), dtb.begin(), dtb.end());
-  rom.resize((rom.size() / align + 1) * align);
+  const int align = 0x1000;
+  rom.resize((rom.size() + align - 1) / align * align);
 
   boot_rom.reset(new rom_device_t(rom));
   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());