Add --gdb-port

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index db08cb2cfbf4e154535955b6f3b4be697825e73e..ccaa6c8e1a5ba02e546002f131a0aafe8ecfcf05 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -20,10 +20,10 @@ static void handle_signal(int sig)
   signal(sig, &handle_signal);
 }
 
-sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
+sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
              const std::vector<std::string>& args)
   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
-    current_step(0), current_proc(0), debug(false)
+    current_step(0), current_proc(0), debug(false), gdbserver(NULL)
 {
   signal(SIGINT, &handle_signal);
   // allocate target machine's memory, shrinking it as necessary
@@ -43,8 +43,10 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
 
   debug_mmu = new mmu_t(this, NULL);
 
-  for (size_t i = 0; i < procs.size(); i++)
+  for (size_t i = 0; i < procs.size(); i++) {
     procs[i] = new processor_t(isa, this, i);
+    procs[i]->set_halted(halted, HR_CMDLINE);
+  }
 
   rtc.reset(new rtc_t(procs));
   make_config_string();
@@ -68,6 +70,9 @@ int sim_t::run()
       interactive();
     else
       step(INTERLEAVE);
+    if (gdbserver) {
+        gdbserver->handle();
+    }
   }
   return htif->exit_code();
 }