Add --gdb-port

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index edbe2ed0a71f1ffe7c7d52985b1bb0a27bd316a9..ccaa6c8e1a5ba02e546002f131a0aafe8ecfcf05 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -20,10 +20,10 @@ static void handle_signal(int sig)
   signal(sig, &handle_signal);
 }
 
-sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
+sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
              const std::vector<std::string>& args)
   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
-    current_step(0), current_proc(0), debug(false)
+    current_step(0), current_proc(0), debug(false), gdbserver(NULL)
 {
   signal(SIGINT, &handle_signal);
   // allocate target machine's memory, shrinking it as necessary
@@ -43,8 +43,10 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
 
   debug_mmu = new mmu_t(this, NULL);
 
-  for (size_t i = 0; i < procs.size(); i++)
+  for (size_t i = 0; i < procs.size(); i++) {
     procs[i] = new processor_t(isa, this, i);
+    procs[i]->set_halted(halted, HR_CMDLINE);
+  }
 
   rtc.reset(new rtc_t(procs));
   make_config_string();
@@ -68,6 +70,9 @@ int sim_t::run()
       interactive();
     else
       step(INTERLEAVE);
+    if (gdbserver) {
+        gdbserver->handle();
+    }
   }
   return htif->exit_code();
 }
@@ -102,13 +107,6 @@ bool sim_t::running()
   return false;
 }
 
-void sim_t::stop()
-{
-  procs[0]->state.tohost = 1;
-  while (htif->tick())
-    ;
-}
-
 void sim_t::set_debug(bool value)
 {
   debug = value;
@@ -149,11 +147,13 @@ bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 
 void sim_t::make_config_string()
 {
-  reg_t boot_rom_addr = DEFAULT_RSTVEC;
-  reg_t boot_rom_size = 0x2000;
-  reg_t rtc_addr = boot_rom_addr + boot_rom_size;
+  reg_t rtc_addr = EXT_IO_BASE;
   bus.add_device(rtc_addr, rtc.get());
 
+  const int align = 0x1000;
+  reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
+  reg_t cpu_size = align;
+
   uint32_t reset_vec[8] = {
     0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
     0x00028067,                         //   jump straight to DRAM_BASE
@@ -161,7 +161,7 @@ void sim_t::make_config_string()
     0,                                  // config string pointer
     0, 0, 0, 0                          // trap vector
   };
-  reset_vec[3] = boot_rom_addr + sizeof(reset_vec); // config string pointer
+  reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer
 
   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 
@@ -187,16 +187,18 @@ void sim_t::make_config_string()
         "    " << "0 {\n" << // hart 0 on core i
         "      isa " << procs[i]->isa_string << ";\n"
         "      timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n"
+        "      ipi 0x" << cpu_addr << ";\n"
         "    };\n"
         "  };\n";
+    bus.add_device(cpu_addr, procs[i]);
+    cpu_addr += cpu_size;
   }
   s <<  "};\n";
 
   config_string = s.str();
   rom.insert(rom.end(), config_string.begin(), config_string.end());
-  assert(rom.size() < boot_rom_size);
-  rom.resize(boot_rom_size);
+  rom.resize((rom.size() / align + 1) * align);
 
   boot_rom.reset(new rom_device_t(rom));
-  bus.add_device(boot_rom_addr, boot_rom.get());
+  bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 }