Add an option (-l) to display a log of execution in non-interactive mode.

[riscv-isa-sim.git] / riscv / sim.h

diff --git a/riscv/sim.h b/riscv/sim.h
index 6d2ac9be43aa46ea5724bc4b357267e7a12f694d..1f43cee4105f8c8923d81fb727d299f67d844576 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -1,46 +1,88 @@
+// See LICENSE for license details.
+
 #ifndef _RISCV_SIM_H
 #define _RISCV_SIM_H
 
 #include <vector>
 #include <string>
+#include <memory>
 #include "processor.h"
+#include "mmu.h"
 
-const int MEMSIZE = 0x7D000000;
+class htif_isasim_t;
 
+// this class encapsulates the processors and memory in a RISC-V machine.
 class sim_t
 {
 public:
-  sim_t(int _nprocs, size_t _memsz);
+  sim_t(const char* isa, size_t _nprocs, size_t mem_mb,
+        const std::vector<std::string>& htif_args);
   ~sim_t();
-  void load_elf(const char* fn);
-  void run(bool debug);
 
-private:
-  processor_t* procs;
-  int nprocs;
+  // run the simulation to completion
+  int run();
+  bool running();
+  void stop();
+  void set_debug(bool value);
+  void set_log(bool value);
+  void set_histogram(bool value);
+  void set_procs_debug(bool value);
+  htif_isasim_t* get_htif() { return htif.get(); }
 
-  char* mem;
-  size_t memsz;
+  // deliver an IPI to a specific processor
+  void send_ipi(reg_t who);
 
-  void step_all(size_t n, size_t interleave, bool noisy);
+  // returns the number of processors in this simulator
+  size_t num_cores() { return procs.size(); }
+  processor_t* get_core(size_t i) { return procs.at(i); }
 
-  void interactive_quit(const std::vector<std::string>& args);
+  // read one of the system control registers
+  reg_t get_scr(int which);
 
-  void interactive_run(const std::vector<std::string>& args, bool noisy);
-  void interactive_run_noisy(const std::vector<std::string>& args);
-  void interactive_run_silent(const std::vector<std::string>& args);
+private:
+  std::unique_ptr<htif_isasim_t> htif;
+  char* mem; // main memory
+  size_t memsz; // memory size in bytes
+  mmu_t* debug_mmu;  // debug port into main memory
+  std::vector<processor_t*> procs;
 
-  void interactive_run_proc(const std::vector<std::string>& args, bool noisy);
-  void interactive_run_proc_noisy(const std::vector<std::string>& args);
-  void interactive_run_proc_silent(const std::vector<std::string>& args);
+  processor_t* get_core(const std::string& i);
+  void step(size_t n); // step through simulation
+  static const size_t INTERLEAVE = 5000;
+  static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
+  reg_t rtc;
+  size_t current_step;
+  size_t current_proc;
+  bool debug;
+  bool log;
+  bool histogram_enabled; // provide a histogram of PCs
 
-  void interactive_reg(const std::vector<std::string>& args);
-  void interactive_mem(const std::vector<std::string>& args);
-  void interactive_until(const std::vector<std::string>& args);
+  // presents a prompt for introspection into the simulation
+  void interactive();
 
+  // functions that help implement interactive()
+  void interactive_help(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_quit(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
+  void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_pc(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_mem(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_str(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_until(const std::string& cmd, const std::vector<std::string>& args);
   reg_t get_reg(const std::vector<std::string>& args);
+  reg_t get_freg(const std::vector<std::string>& args);
   reg_t get_mem(const std::vector<std::string>& args);
   reg_t get_pc(const std::vector<std::string>& args);
+  reg_t get_tohost(const std::vector<std::string>& args);
+
+  friend class htif_isasim_t;
+  friend class processor_t;
 };
 
+extern volatile bool ctrlc_pressed;
+
 #endif