Implement debug havereset bits

[riscv-isa-sim.git] / riscv / sim.h

diff --git a/riscv/sim.h b/riscv/sim.h
index 9a0a10b2569ba4a6aa8190fb5a540108f5a85a72..257de5ba85acc8fbbea5416e0d2efcb0e91953a4 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -24,6 +24,8 @@ public:
   // used for MMIO addresses
   virtual bool mmio_load(reg_t addr, size_t len, uint8_t* bytes) = 0;
   virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0;
+  // Callback for processors to let the simulation know they were reset.
+  virtual void proc_reset(unsigned id) = 0;
 };
 
 // this class encapsulates the processors and memory in a RISC-V machine.
@@ -49,6 +51,9 @@ public:
   processor_t* get_core(size_t i) { return procs.at(i); }
   unsigned nprocs() const { return procs.size(); }
 
+  // Callback for processors to let the simulation know they were reset.
+  void proc_reset(unsigned id);
+
 private:
   std::vector<std::pair<reg_t, mem_t*>> mems;
   mmu_t* debug_mmu;  // debug port into main memory