unify interactive core processing

[riscv-isa-sim.git] / riscv / sim.h

diff --git a/riscv/sim.h b/riscv/sim.h
index 9b8f6e0f90582011493e72484564aeb436d06453..8f7718a028332765ad7ae7c9259db5543477c314 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -45,6 +45,7 @@ private:
   mmu_t* debug_mmu;  // debug port into main memory
   std::vector<processor_t*> procs;
 
+  processor_t* get_core(const std::string& i);
   void step(size_t n); // step through simulation
   static const size_t INTERLEAVE = 5000;
   static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core