add I$/D$/L2$ simulators

[riscv-isa-sim.git] / riscv / sim.h

diff --git a/riscv/sim.h b/riscv/sim.h
index 085eb68cf02169fe53b0f3c91741feb8c413241c..aed4e87f67dc39db4db8f5b70dfafc6727ba9d7e 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -23,6 +23,7 @@ public:
 
   // returns the number of processors in this simulator
   size_t num_cores() { return procs.size(); }
+  processor_t* get_core(size_t i) { return procs[i]; }
 
   // read one of the system control registers
   reg_t get_scr(int which);