#include "processor.h"
#include "devices.h"
#include "debug_module.h"
+#include "simif.h"
#include <fesvr/htif.h>
#include <fesvr/context.h>
#include <vector>
class remote_bitbang_t;
// this class encapsulates the processors and memory in a RISC-V machine.
-class sim_t : public htif_t
+class sim_t : public htif_t, public simif_t
{
public:
sim_t(const char* isa, size_t _nprocs, bool halted, reg_t start_pc,
std::vector<std::pair<reg_t, mem_t*>> mems,
- const std::vector<std::string>& args);
+ const std::vector<std::string>& args, const std::vector<int> hartids,
+ unsigned progsize, unsigned max_bus_master_bits, bool require_authentication);
~sim_t();
// run the simulation to completion
void set_log(bool value);
void set_histogram(bool value);
void set_procs_debug(bool value);
+ void set_dtb_enabled(bool value) {
+ this->dtb_enabled = value;
+ }
void set_remote_bitbang(remote_bitbang_t* remote_bitbang) {
this->remote_bitbang = remote_bitbang;
}
processor_t* get_core(size_t i) { return procs.at(i); }
unsigned nprocs() const { return procs.size(); }
- debug_module_t debug_module;
+ // Callback for processors to let the simulation know they were reset.
+ void proc_reset(unsigned id);
private:
std::vector<std::pair<reg_t, mem_t*>> mems;
bool debug;
bool log;
bool histogram_enabled; // provide a histogram of PCs
+ bool dtb_enabled;
remote_bitbang_t* remote_bitbang;
// memory-mapped I/O routines
friend class processor_t;
friend class mmu_t;
+ friend class debug_module_t;
// htif
friend void sim_thread_main(void*);
void write_chunk(addr_t taddr, size_t len, const void* src);
size_t chunk_align() { return 8; }
size_t chunk_max_size() { return 8; }
+
+public:
+ // Initialize this after procs, because in debug_module_t::reset() we
+ // enumerate processors, which segfaults if procs hasn't been initialized
+ // yet.
+ debug_module_t debug_module;
};
extern volatile bool ctrlc_pressed;