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[riscv-isa-sim.git] / riscv / sim.h

diff --git a/riscv/sim.h b/riscv/sim.h
index 34ed6e8a2b0a1433c9f31c363a36d3fbdb26ffb1..c8ba4073c02157538060c42cc4c9dd86ba98826c 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -3,55 +3,75 @@
 #ifndef _RISCV_SIM_H
 #define _RISCV_SIM_H
 
+#include "processor.h"
+#include "devices.h"
+#include "debug_module.h"
+#include <fesvr/htif.h>
+#include <fesvr/context.h>
 #include <vector>
 #include <string>
 #include <memory>
-#include "processor.h"
-#include "mmu.h"
 
-class htif_isasim_t;
+class mmu_t;
+class remote_bitbang_t;
 
 // this class encapsulates the processors and memory in a RISC-V machine.
-class sim_t
+class sim_t : public htif_t
 {
 public:
-  sim_t(size_t _nprocs, size_t mem_mb, const std::vector<std::string>& htif_args);
+  sim_t(const char* isa, size_t _nprocs, size_t mem_mb, bool halted,
+        const std::vector<std::string>& args);
   ~sim_t();
 
   // run the simulation to completion
   int run();
-  bool running();
-  void stop();
   void set_debug(bool value);
+  void set_log(bool value);
+  void set_histogram(bool value);
   void set_procs_debug(bool value);
-
-  // deliver an IPI to a specific processor
-  void send_ipi(reg_t who);
-
-  // returns the number of processors in this simulator
-  size_t num_cores() { return procs.size(); }
-  processor_t* get_core(size_t i) { return procs[i]; }
-
-  // read one of the system control registers
-  reg_t get_scr(int which);
+  void set_remote_bitbang(remote_bitbang_t* remote_bitbang) {
+    this->remote_bitbang = remote_bitbang;
+  }
+  const char* get_config_string() { return config_string.c_str(); }
+  processor_t* get_core(size_t i) { return procs.at(i); }
 
 private:
-  std::auto_ptr<htif_isasim_t> htif;
   char* mem; // main memory
   size_t memsz; // memory size in bytes
   mmu_t* debug_mmu;  // debug port into main memory
   std::vector<processor_t*> procs;
+  std::string config_string;
+  std::unique_ptr<rom_device_t> boot_rom;
+  std::unique_ptr<rtc_t> rtc;
+  bus_t bus;
+  debug_module_t debug_module;
 
+  processor_t* get_core(const std::string& i);
   void step(size_t n); // step through simulation
   static const size_t INTERLEAVE = 5000;
+  static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
   size_t current_step;
   size_t current_proc;
   bool debug;
+  bool log;
+  bool histogram_enabled; // provide a histogram of PCs
+  remote_bitbang_t* remote_bitbang;
+
+  // memory-mapped I/O routines
+  bool addr_is_mem(reg_t addr) {
+    return addr >= DRAM_BASE && addr < DRAM_BASE + memsz;
+  }
+  char* addr_to_mem(reg_t addr) { return mem + addr - DRAM_BASE; }
+  reg_t mem_to_addr(char* x) { return x - mem + DRAM_BASE; }
+  bool mmio_load(reg_t addr, size_t len, uint8_t* bytes);
+  bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes);
+  void make_config_string();
 
   // presents a prompt for introspection into the simulation
   void interactive();
 
   // functions that help implement interactive()
+  void interactive_help(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_quit(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
   void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args);
@@ -59,6 +79,7 @@ private:
   void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_pc(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_mem(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_str(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_until(const std::string& cmd, const std::vector<std::string>& args);
@@ -66,9 +87,22 @@ private:
   reg_t get_freg(const std::vector<std::string>& args);
   reg_t get_mem(const std::vector<std::string>& args);
   reg_t get_pc(const std::vector<std::string>& args);
-  reg_t get_tohost(const std::vector<std::string>& args);
 
-  friend class htif_isasim_t;
+  friend class processor_t;
+  friend class mmu_t;
+
+  // htif
+  friend void sim_thread_main(void*);
+  void main();
+
+  context_t* host;
+  context_t target;
+  void reset() { }
+  void idle();
+  void read_chunk(addr_t taddr, size_t len, void* dst);
+  void write_chunk(addr_t taddr, size_t len, const void* src);
+  size_t chunk_align() { return 8; }
+  size_t chunk_max_size() { return 8; }
 };
 
 extern volatile bool ctrlc_pressed;