OpenOCD connects, and sends some data that we receive.

[riscv-isa-sim.git] / riscv / sim.h

diff --git a/riscv/sim.h b/riscv/sim.h
index cac1dafba4e7970626dbd8efc881abd4bdc1849a..c8ba4073c02157538060c42cc4c9dd86ba98826c 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -3,41 +3,39 @@
 #ifndef _RISCV_SIM_H
 #define _RISCV_SIM_H
 
+#include "processor.h"
+#include "devices.h"
+#include "debug_module.h"
+#include <fesvr/htif.h>
+#include <fesvr/context.h>
 #include <vector>
 #include <string>
 #include <memory>
-#include "processor.h"
-#include "devices.h"
-#include "gdbserver.h"
 
-class htif_isasim_t;
 class mmu_t;
+class remote_bitbang_t;
 
 // this class encapsulates the processors and memory in a RISC-V machine.
-class sim_t
+class sim_t : public htif_t
 {
 public:
-  sim_t(const char* isa, size_t _nprocs, size_t mem_mb,
-        const std::vector<std::string>& htif_args);
+  sim_t(const char* isa, size_t _nprocs, size_t mem_mb, bool halted,
+        const std::vector<std::string>& args);
   ~sim_t();
 
   // run the simulation to completion
   int run();
-  bool running();
   void set_debug(bool value);
   void set_log(bool value);
   void set_histogram(bool value);
   void set_procs_debug(bool value);
-  void set_gdbserver(gdbserver_t* gdbserver) { this->gdbserver = gdbserver; }
-  htif_isasim_t* get_htif() { return htif.get(); }
+  void set_remote_bitbang(remote_bitbang_t* remote_bitbang) {
+    this->remote_bitbang = remote_bitbang;
+  }
   const char* get_config_string() { return config_string.c_str(); }
-
-  // returns the number of processors in this simulator
-  size_t num_cores() { return procs.size(); }
   processor_t* get_core(size_t i) { return procs.at(i); }
 
 private:
-  std::unique_ptr<htif_isasim_t> htif;
   char* mem; // main memory
   size_t memsz; // memory size in bytes
   mmu_t* debug_mmu;  // debug port into main memory
@@ -46,6 +44,7 @@ private:
   std::unique_ptr<rom_device_t> boot_rom;
   std::unique_ptr<rtc_t> rtc;
   bus_t bus;
+  debug_module_t debug_module;
 
   processor_t* get_core(const std::string& i);
   void step(size_t n); // step through simulation
@@ -56,7 +55,7 @@ private:
   bool debug;
   bool log;
   bool histogram_enabled; // provide a histogram of PCs
-  gdbserver_t* gdbserver;
+  remote_bitbang_t* remote_bitbang;
 
   // memory-mapped I/O routines
   bool addr_is_mem(reg_t addr) {
@@ -89,9 +88,21 @@ private:
   reg_t get_mem(const std::vector<std::string>& args);
   reg_t get_pc(const std::vector<std::string>& args);
 
-  friend class htif_isasim_t;
   friend class processor_t;
   friend class mmu_t;
+
+  // htif
+  friend void sim_thread_main(void*);
+  void main();
+
+  context_t* host;
+  context_t target;
+  void reset() { }
+  void idle();
+  void read_chunk(addr_t taddr, size_t len, void* dst);
+  void write_chunk(addr_t taddr, size_t len, const void* src);
+  size_t chunk_align() { return 8; }
+  size_t chunk_max_size() { return 8; }
 };
 
 extern volatile bool ctrlc_pressed;