Support setting ISA/subsets with --isa flag

[riscv-isa-sim.git] / riscv / sim.h

diff --git a/riscv/sim.h b/riscv/sim.h
index 34ed6e8a2b0a1433c9f31c363a36d3fbdb26ffb1..ca1ad6f544b9fb100f741f8340ad2d234574625c 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -15,7 +15,8 @@ class htif_isasim_t;
 class sim_t
 {
 public:
-  sim_t(size_t _nprocs, size_t mem_mb, const std::vector<std::string>& htif_args);
+  sim_t(const char* isa, size_t _nprocs, size_t mem_mb,
+        const std::vector<std::string>& htif_args);
   ~sim_t();
 
   // run the simulation to completion
@@ -23,20 +24,22 @@ public:
   bool running();
   void stop();
   void set_debug(bool value);
+  void set_histogram(bool value);
   void set_procs_debug(bool value);
+  htif_isasim_t* get_htif() { return htif.get(); }
 
   // deliver an IPI to a specific processor
   void send_ipi(reg_t who);
 
   // returns the number of processors in this simulator
   size_t num_cores() { return procs.size(); }
-  processor_t* get_core(size_t i) { return procs[i]; }
+  processor_t* get_core(size_t i) { return procs.at(i); }
 
   // read one of the system control registers
   reg_t get_scr(int which);
 
 private:
-  std::auto_ptr<htif_isasim_t> htif;
+  std::unique_ptr<htif_isasim_t> htif;
   char* mem; // main memory
   size_t memsz; // memory size in bytes
   mmu_t* debug_mmu;  // debug port into main memory
@@ -47,6 +50,7 @@ private:
   size_t current_step;
   size_t current_proc;
   bool debug;
+  bool histogram_enabled; // provide a histogram of PCs
 
   // presents a prompt for introspection into the simulation
   void interactive();
@@ -69,6 +73,7 @@ private:
   reg_t get_tohost(const std::vector<std::string>& args);
 
   friend class htif_isasim_t;
+  friend class processor_t;
 };
 
 extern volatile bool ctrlc_pressed;