Support setting ISA/subsets with --isa flag

[riscv-isa-sim.git] / riscv / sim.h

diff --git a/riscv/sim.h b/riscv/sim.h
index aed4e87f67dc39db4db8f5b70dfafc6727ba9d7e..ca1ad6f544b9fb100f741f8340ad2d234574625c 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -1,8 +1,11 @@
+// See LICENSE for license details.
+
 #ifndef _RISCV_SIM_H
 #define _RISCV_SIM_H
 
 #include <vector>
 #include <string>
+#include <memory>
 #include "processor.h"
 #include "mmu.h"
 
@@ -12,38 +15,42 @@ class htif_isasim_t;
 class sim_t
 {
 public:
-  sim_t(int _nprocs, int mem_mb, const std::vector<std::string>& htif_args);
+  sim_t(const char* isa, size_t _nprocs, size_t mem_mb,
+        const std::vector<std::string>& htif_args);
   ~sim_t();
 
   // run the simulation to completion
-  void run(bool debug);
+  int run();
+  bool running();
+  void stop();
+  void set_debug(bool value);
+  void set_histogram(bool value);
+  void set_procs_debug(bool value);
+  htif_isasim_t* get_htif() { return htif.get(); }
 
   // deliver an IPI to a specific processor
   void send_ipi(reg_t who);
 
   // returns the number of processors in this simulator
   size_t num_cores() { return procs.size(); }
-  processor_t* get_core(size_t i) { return procs[i]; }
+  processor_t* get_core(size_t i) { return procs.at(i); }
 
   // read one of the system control registers
   reg_t get_scr(int which);
 
 private:
-  htif_isasim_t* htif;
-
-  // main memory, shared between processors
-  char* mem;
+  std::unique_ptr<htif_isasim_t> htif;
+  char* mem; // main memory
   size_t memsz; // memory size in bytes
-  mmu_t* mmu; // debug port into main memory
-
-  // processors
+  mmu_t* debug_mmu;  // debug port into main memory
   std::vector<processor_t*> procs;
 
-  // run each processor for n instructions; interleave instructions are
-  // run on a processor before moving on to the next processor.
-  // interleave must divide n.
-  // if noisy, print out the instructions as they execute.
-  void step_all(size_t n, size_t interleave, bool noisy);
+  void step(size_t n); // step through simulation
+  static const size_t INTERLEAVE = 5000;
+  size_t current_step;
+  size_t current_proc;
+  bool debug;
+  bool histogram_enabled; // provide a histogram of PCs
 
   // presents a prompt for introspection into the simulation
   void interactive();
@@ -53,9 +60,6 @@ private:
   void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
   void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args);
-  void interactive_run_proc(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
-  void interactive_run_proc_noisy(const std::string& cmd, const std::vector<std::string>& args);
-  void interactive_run_proc_silent(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
@@ -69,6 +73,9 @@ private:
   reg_t get_tohost(const std::vector<std::string>& args);
 
   friend class htif_isasim_t;
+  friend class processor_t;
 };
 
+extern volatile bool ctrlc_pressed;
+
 #endif