Add --dump-config-string flag

[riscv-isa-sim.git] / riscv / sim.h

diff --git a/riscv/sim.h b/riscv/sim.h
index 1f43cee4105f8c8923d81fb727d299f67d844576..d8f39e2e73ed9e7637bf55834dc303d00a2cf1ae 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -8,6 +8,7 @@
 #include <memory>
 #include "processor.h"
 #include "mmu.h"
+#include "devices.h"
 
 class htif_isasim_t;
 
@@ -28,9 +29,7 @@ public:
   void set_histogram(bool value);
   void set_procs_debug(bool value);
   htif_isasim_t* get_htif() { return htif.get(); }
-
-  // deliver an IPI to a specific processor
-  void send_ipi(reg_t who);
+  const char* get_config_string() { return &config_string->contents()[0]; }
 
   // returns the number of processors in this simulator
   size_t num_cores() { return procs.size(); }
@@ -45,18 +44,26 @@ private:
   size_t memsz; // memory size in bytes
   mmu_t* debug_mmu;  // debug port into main memory
   std::vector<processor_t*> procs;
+  std::unique_ptr<rom_device_t> config_string;
+  std::unique_ptr<rtc_t> rtc;
+  reg_t config_string_addr;
+  bus_t bus;
 
   processor_t* get_core(const std::string& i);
   void step(size_t n); // step through simulation
   static const size_t INTERLEAVE = 5000;
   static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
-  reg_t rtc;
   size_t current_step;
   size_t current_proc;
   bool debug;
   bool log;
   bool histogram_enabled; // provide a histogram of PCs
 
+  // memory-mapped I/O routines
+  bool mmio_load(reg_t addr, size_t len, uint8_t* bytes);
+  bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes);
+  void make_config_string();
+
   // presents a prompt for introspection into the simulation
   void interactive();
 
@@ -81,6 +88,7 @@ private:
 
   friend class htif_isasim_t;
   friend class processor_t;
+  friend class mmu_t;
 };
 
 extern volatile bool ctrlc_pressed;