Add --dump-config-string flag

[riscv-isa-sim.git] / riscv / sim.h

diff --git a/riscv/sim.h b/riscv/sim.h
index 34ed6e8a2b0a1433c9f31c363a36d3fbdb26ffb1..d8f39e2e73ed9e7637bf55834dc303d00a2cf1ae 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -8,6 +8,7 @@
 #include <memory>
 #include "processor.h"
 #include "mmu.h"
+#include "devices.h"
 
 class htif_isasim_t;
 
@@ -15,7 +16,8 @@ class htif_isasim_t;
 class sim_t
 {
 public:
-  sim_t(size_t _nprocs, size_t mem_mb, const std::vector<std::string>& htif_args);
+  sim_t(const char* isa, size_t _nprocs, size_t mem_mb,
+        const std::vector<std::string>& htif_args);
   ~sim_t();
 
   // run the simulation to completion
@@ -23,35 +25,50 @@ public:
   bool running();
   void stop();
   void set_debug(bool value);
+  void set_log(bool value);
+  void set_histogram(bool value);
   void set_procs_debug(bool value);
-
-  // deliver an IPI to a specific processor
-  void send_ipi(reg_t who);
+  htif_isasim_t* get_htif() { return htif.get(); }
+  const char* get_config_string() { return &config_string->contents()[0]; }
 
   // returns the number of processors in this simulator
   size_t num_cores() { return procs.size(); }
-  processor_t* get_core(size_t i) { return procs[i]; }
+  processor_t* get_core(size_t i) { return procs.at(i); }
 
   // read one of the system control registers
   reg_t get_scr(int which);
 
 private:
-  std::auto_ptr<htif_isasim_t> htif;
+  std::unique_ptr<htif_isasim_t> htif;
   char* mem; // main memory
   size_t memsz; // memory size in bytes
   mmu_t* debug_mmu;  // debug port into main memory
   std::vector<processor_t*> procs;
+  std::unique_ptr<rom_device_t> config_string;
+  std::unique_ptr<rtc_t> rtc;
+  reg_t config_string_addr;
+  bus_t bus;
 
+  processor_t* get_core(const std::string& i);
   void step(size_t n); // step through simulation
   static const size_t INTERLEAVE = 5000;
+  static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
   size_t current_step;
   size_t current_proc;
   bool debug;
+  bool log;
+  bool histogram_enabled; // provide a histogram of PCs
+
+  // memory-mapped I/O routines
+  bool mmio_load(reg_t addr, size_t len, uint8_t* bytes);
+  bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes);
+  void make_config_string();
 
   // presents a prompt for introspection into the simulation
   void interactive();
 
   // functions that help implement interactive()
+  void interactive_help(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_quit(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
   void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args);
@@ -59,6 +76,7 @@ private:
   void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_pc(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_mem(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_str(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_until(const std::string& cmd, const std::vector<std::string>& args);
@@ -69,6 +87,8 @@ private:
   reg_t get_tohost(const std::vector<std::string>& args);
 
   friend class htif_isasim_t;
+  friend class processor_t;
+  friend class mmu_t;
 };
 
 extern volatile bool ctrlc_pressed;