refactor disassembler, and add hwacha disassembler

[riscv-isa-sim.git] / riscv / sim.h

diff --git a/riscv/sim.h b/riscv/sim.h
index bcb7c1c9c7361abfc0cce39a6f2748d827bfd150..e827087ebd784729f3775af4378b91dd879d42e5 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -22,7 +22,8 @@ public:
   void run();
   bool running();
   void stop();
-  void set_debug(bool value) { debug = value; }
+  void set_debug(bool value);
+  void set_procs_debug(bool value);
 
   // deliver an IPI to a specific processor
   void send_ipi(reg_t who);
@@ -41,7 +42,7 @@ private:
   mmu_t* debug_mmu;  // debug port into main memory
   std::vector<processor_t*> procs;
 
-  void step(size_t n, bool noisy); // step through simulation
+  void step(size_t n); // step through simulation
   static const size_t INTERLEAVE = 5000;
   size_t current_step;
   size_t current_proc;