big reorganisation to support twin-predication

[riscv-isa-sim.git] / riscv / sv.cc

diff --git a/riscv/sv.cc b/riscv/sv.cc
index 90ef35426581b2cafdfce6c78591b98811c61bcc..7f7846ae8d248f4165a93705ce83d8aaa135992b 100644 (file)
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -165,3 +165,9 @@ uint64_t sv_insn_t::predicated(uint64_t reg, int offs, uint64_t pred)
     return 0;
 }
 
+bool sv_insn_t::stop_vloop(void)
+{
+    return (p->get_state()->vl == 0) || !vloop_continue;
+}
+
+