reorganise twin-predication

[riscv-isa-sim.git] / riscv / sv.cc

diff --git a/riscv/sv.cc b/riscv/sv.cc
index 1a16730175765780a49f10264e841048db975478..9cc46507e524b5dfafd3d917762841426bd8dd0e 100644 (file)
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -66,7 +66,7 @@ bool sv_insn_t::sv_check_reg(bool intreg, uint64_t reg)
  * of SV.  it's "supposed" to "just" be a vectorisation API. it isn't:
  * it's quite a bit more.
  */
-uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs, int &newoffs)
+uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs)
 {
   // okaay so first determine which map to use.  intreg is passed
   // in (ultimately) from id_regs.py's examination of the use of
@@ -78,9 +78,9 @@ uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs, int &newoffs)
   // is not being "redirected", so just return the actual reg.
   if (!r->active)
   {
-    vloop_continue = false;
     return reg; // not active: return as-is
   }
+  vloop_continue = true;
 
   // next we go through the lookup table.  *THIS* is why the
   // sv_reg_entry table is 32 entries (5-bit) *NOT* 6 bits
@@ -92,19 +92,15 @@ uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs, int &newoffs)
   // we return the re-mapped register...
   if (!r->isvec) // scalar
   {
-    vloop_continue = false;
     return reg; 
   }
+  vloop_continue = true;
 
   // aaand now, as it's a "vector", FINALLY we can add on the loop-offset
   // which was passed in to the sv_insn_t constructor (by reference)
   // and, at last, we have "parallelism" a la contiguous registers.
   reg += voffs; // wheww :)
 
-  // however... before returning, we increment the loop-offset for
-  // this particular register, so that on the next loop the next
-  // contiguous register will be used.
-  newoffs = voffs + 1;
   return reg;
 }
 
@@ -165,3 +161,9 @@ uint64_t sv_insn_t::predicated(uint64_t reg, int offs, uint64_t pred)
     return 0;
 }
 
+bool sv_insn_t::stop_vloop(void)
+{
+    return (p->get_state()->vl == 0) || !vloop_continue;
+}
+
+