* of SV. it's "supposed" to "just" be a vectorisation API. it isn't:
* it's quite a bit more.
*/
-uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs, int &newoffs)
+uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs)
{
// okaay so first determine which map to use. intreg is passed
// in (ultimately) from id_regs.py's examination of the use of
// is not being "redirected", so just return the actual reg.
if (!r->active)
{
- vloop_continue = false;
return reg; // not active: return as-is
}
+ vloop_continue = true;
// next we go through the lookup table. *THIS* is why the
// sv_reg_entry table is 32 entries (5-bit) *NOT* 6 bits
// we return the re-mapped register...
if (!r->isvec) // scalar
{
- vloop_continue = false;
return reg;
}
+ vloop_continue = true;
// aaand now, as it's a "vector", FINALLY we can add on the loop-offset
// which was passed in to the sv_insn_t constructor (by reference)
// and, at last, we have "parallelism" a la contiguous registers.
reg += voffs; // wheww :)
- // however... before returning, we increment the loop-offset for
- // this particular register, so that on the next loop the next
- // contiguous register will be used.
- newoffs = voffs + 1;
return reg;
}
*/
reg_t sv_insn_t::predicate(uint64_t reg, bool intreg, bool &zeroing)
{
+ sv_reg_entry *pr = get_regentry(reg, intreg);
+ if (!pr->active)
+ {
+ return ~0x0; // *REGISTER* not active: return all-1s (unconditional "on")
+ }
sv_pred_entry *r = get_predentry(reg, intreg);
if (!r->active)
{
- return ~0x0; // not active: return all-1s (unconditional "on")
+ return ~0x0; // *PREDICATION* not active: return all-1s (unconditional "on")
}
zeroing = r->zero;
reg = r->regidx;
return 0;
}
+bool sv_insn_t::stop_vloop(void)
+{
+ return (p->get_state()->vl == 0) || !vloop_continue;
+}
+
+