reorganise twin-predication

[riscv-isa-sim.git] / riscv / sv_decode.h

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index e8eee2674d5391fb7f6299710dce9f13ac87ba3e..7bffe1b47934c6f611a72f5053988cf27ff8d1a0 100644 (file)
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -5,19 +5,87 @@
 
 #include "sv.h"
 #include "decode.h"
+#include "processor.h"
+
+#define REG_RD 0x1
+#define REG_RS1 0x2
+#define REG_RS2 0x4
+#define REG_RS3 0x8
+#define REG_RVC_RS1 0x10
+#define REG_RVC_RS2 0x20
+#define REG_RVC_RS1S 0x40
+#define REG_RVC_RS2S 0x80
+
 
 class sv_insn_t: public insn_t
 {
 public:
-  sv_insn_t(insn_bits_t bits) : insn_t(bits) {}
-  uint64_t rd () { return remap(insn_t::rd()); }
-  uint64_t rs1() { return remap(insn_t::rs1()); }
-  uint64_t rs2() { return remap(insn_t::rs2()); }
-  uint64_t rs3() { return remap(insn_t::rs3()); }
+  sv_insn_t(processor_t *pr, insn_bits_t bits, unsigned int f,
+            uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
+            int &o_rd, int &o_rs1, int &o_rs2, int &o_rs3) :
+            insn_t(bits), p(pr), vloop_continue(false), fimap(f),
+            offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
+            prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3) {}
+  uint64_t rd () { return predicated(_rd (), offs_rd, prd); }
+  uint64_t rs1() { return predicated(_rs1(), offs_rs1, prs1); }
+  uint64_t rs2() { return predicated(_rs2(), offs_rs2, prs2); }
+  uint64_t rs3() { return predicated(_rs3(), offs_rs3, prs3); }
+  uint64_t rvc_rs1 () { return predicated(_rvc_rs1 (), offs_rs1, prs1); }
+  uint64_t rvc_rs1s() { return predicated(_rvc_rs1s(), offs_rs1, prs1); }
+  uint64_t rvc_rs2 () { return predicated(_rvc_rs2 (), offs_rs2, prs2); }
+  uint64_t rvc_rs2s() { return predicated(_rvc_rs2s(), offs_rs2, prs2); }
+
+  uint64_t _rd () { return _remap(insn_t::rd (), fimap & REG_RD , offs_rd); }
+  uint64_t _rs1() { return _remap(insn_t::rs1(), fimap & REG_RS1, offs_rs1); }
+  uint64_t _rs2() { return _remap(insn_t::rs2(), fimap & REG_RS2, offs_rs2); }
+  uint64_t _rs3() { return _remap(insn_t::rs3(), fimap & REG_RS3, offs_rs3); }
+  uint64_t _rvc_rs1 () { return _remap(insn_t::rvc_rs1(), fimap & REG_RVC_RS1,
+                                       offs_rs1); }
+  uint64_t _rvc_rs1s() { return _remap(insn_t::rvc_rs1s(), fimap & REG_RVC_RS1S,
+                                       offs_rs1); }
+  uint64_t _rvc_rs2 () { return _remap(insn_t::rvc_rs2(), fimap & REG_RVC_RS2,
+                                       offs_rs2); }
+  uint64_t _rvc_rs2s() { return _remap(insn_t::rvc_rs2s(), fimap & REG_RVC_RS2S,
+                                       offs_rs2); }
+
+  bool sv_check_reg(bool intreg, uint64_t reg);
+  sv_reg_entry* get_regentry(uint64_t reg, bool isint);
+  sv_pred_entry* get_predentry(uint64_t reg, bool isint);
+  reg_t predicate(uint64_t reg, bool isint, bool &zeroing);
+
+  void reset_vloop_check(void) { vloop_continue = false; }
+  bool stop_vloop(void);
+
+  processor_t *p;
 private:
+  bool vloop_continue;
+  unsigned int fimap;
+  int &offs_rd;
+  int &offs_rs1;
+  int &offs_rs2;
+  int &offs_rs3;
+  uint64_t &prd;
+  uint64_t &prs1;
+  uint64_t &prs2;
+  uint64_t &prs3;
+
   // remaps the register through the lookup table.
   // will need to take the current loop index/offset somehow
-  uint64_t remap(uint64_t reg) { return reg; } // TODO
+  uint64_t remap(uint64_t reg, bool isint, int &offs);
+
+  // cached version of remap: if remap is called multiple times
+  // by an emulated instruction it would increment the loop offset
+  // before it's supposed to.
+  uint64_t _remap(uint64_t reg, bool isint, int &offs)
+  {
+    if (sv_check_reg(isint, reg))
+    {
+        vloop_continue = true;
+    }
+    return remap(reg, isint, offs);
+  }
+
+  uint64_t predicated(uint64_t reg, int offs, uint64_t pred);
 };
 
 #endif