get predicated-vectorised branch working

[riscv-isa-sim.git] / riscv / sv_decode.h

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 42ea2e3334e3d6b5c5ca26548216ef65b72b7d7d..98252e78df3dae6d081ae7f80277987ffc0cb60c 100644 (file)
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -60,10 +60,10 @@ public:
                                        offs_rs2); }
 
   void setpc(int xlen, int vlen, reg_t &npc, reg_t addr, uint64_t offs,
-             uint64_t predicate);
+             reg_t *target_reg);
 
   // used for predicated branches. sets bit N if val=true; clears bit N if false
-  uint64_t rd_bitset(uint64_t bit, bool val);
+  uint64_t rd_bitset(reg_t reg, uint64_t bit, bool val);
 
   bool sv_check_reg(bool intreg, uint64_t reg);
   sv_reg_entry* get_regentry(uint64_t reg, bool isint);